 Yannick Reiß
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78077c7b13
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Fix unplanned unnesting bug
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2023-10-21 01:04:44 +02:00 |
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Yannick Reiß
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b21949e38f
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Remove Vivado files
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2023-10-05 15:44:59 +02:00 |
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Yannick Reiß
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8d340be824
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Presentable program
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2023-10-05 15:43:55 +02:00 |
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Yannick Reiß
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041a3e8113
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Removed simulation duration to save time.
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2023-10-05 12:30:40 +02:00 |
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Yannick Reiß
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e27c8a4505
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Change instructions and testbench to test nested loops
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2023-10-05 11:01:35 +02:00 |
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Yannick Reiß
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73d1db32c7
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Change duration of testbench
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2023-10-05 11:01:12 +02:00 |
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Yannick Reiß
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a39b94c26f
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Fix jumping bug
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2023-10-05 08:49:21 +02:00 |
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Yannick Reiß
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b530f66702
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Implement state machine, arith and I/O instructions now working.
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2023-10-04 19:32:13 +02:00 |
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Yannick Reiß
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65c6f85bb9
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Implement testbench for bfpu
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2023-10-04 15:46:23 +02:00 |
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Yannick Reiß
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1b4f753c54
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First working implementation
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2023-10-04 11:27:25 +02:00 |
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Yannick Reiß
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f906a6e4a3
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Implement push and pop in branch
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2023-09-27 20:44:03 +02:00 |
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Yannick Reiß
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30559c81a9
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Implementation of branch, excluding stack
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2023-09-26 20:42:36 +02:00 |
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Yannick Reiß
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180caa0b3c
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Implement program memory
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2023-09-26 14:14:18 +02:00 |
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Yannick Reiß
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d27378e58f
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Implement cell memory
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2023-09-26 12:03:53 +02:00 |
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Yannick Reiß
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51fe976188
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Rushed implementation connecting parts
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2023-09-26 11:37:47 +02:00 |
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Yannick Reiß
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bccd638d2b
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Implement brainfuck ptr
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2023-09-26 11:37:27 +02:00 |
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Yannick Reiß
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74c4ea39b5
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No need for decoder
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2023-09-26 11:37:06 +02:00 |
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Yannick Reiß
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090cd8c07a
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Implement instruction memory
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2023-09-26 11:36:50 +02:00 |
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Yannick Reiß
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75e722b222
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Implement ALU
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2023-09-26 11:34:53 +02:00 |
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Yannick Reiß
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a94cf440c1
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Add constraints for stage 1
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2023-09-26 11:34:40 +02:00 |
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Yannick Reiß
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a8d8a4171a
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Add constraints file
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2023-09-26 07:27:03 +02:00 |
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Yannick Reiß
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b02be01de1
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Add files for fpga
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2023-09-26 07:26:17 +02:00 |