yannickreiss/brainfuck_processor
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Presentable program

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yannickreiss
2023-10-05 15:43:55 +02:00
parent 799b79a899
commit 8d340be824
10 changed files with 815 additions and 5 deletions
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22
fpga/.tmp_logic.md Normal file
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@@ -0,0 +1,22 @@
# Branch redesign
## Skip new logic table
| instruction | cell | skip | nest | | skip |
| ----------- | ---- | ---- | ---- | --- | ---- |
| [ | 0 | 0 | 0 | | 1 |
| [ | 0 | 1 | 0 | | 1 |
| [ | 0 | 1 | 1 | | 1 |
| [ | 1 | 0 | 0 | | 0 |
| [ | 1 | 1 | 0 | | 1 |
| [ | 1 | 1 | 1 | | 1 |
> skip = not ( cell and (skip nor nest) )
| instruction | cell | skip | nest | | skip |
| ----------- | ---- | ---- | ---- | --- | ---- |
| ] | - | 0 | 0 | | 0 |
| ] | - | 1 | 0 | | 0 |
| ] | - | 1 | 1 | | 1 |
> skip = skip and nest

2
fpga/src/instructionMemory.vhd
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@@ -20,7 +20,7 @@ end instructionMemory;
architecture arch of instructionMemory is
type imem is array(0 to 255) of std_logic_vector(2 downto 0);
signal memory : imem := (b"010", b"110", b"000", b"010", b"101", b"001", b"111", others => "000");
signal memory : imem := (b"010",b"110",b"000",b"011",b"110",b"101",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"111",b"001",b"111",b"001",b"111",b"001",b"111",b"001",b"111",others=>"000");
begin
-- Process clk_read
-- clk_read : process (clk) -- runs only, when clk changed