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brainfuck_processor
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Fix unplanned unnesting bug

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Yannick Reiß 2023-10-21 01:04:44 +02:00
parent 02136bd0b9
commit 78077c7b13
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2 changed files with 3 additions and 1 deletions
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2
fpga/src/branch.vhd
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@ -58,7 +58,9 @@ begin
if instruction = "110" then
nested <= std_logic_vector(unsigned(nested) + 1);
end if;
end if;
if state = '1' and skip_internal = '1' then
-- nested loop ended
if instruction = "111" then
nested <= std_logic_vector(unsigned(nested) - 1);

2
fpga/src/instructionMemory.vhd
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@ -20,7 +20,7 @@ end instructionMemory;
architecture arch of instructionMemory is
type imem is array(0 to 255) of std_logic_vector(2 downto 0);
signal memory : imem := (b"010",b"110",b"000",b"011",b"110",b"101",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"111",b"001",b"111",b"001",b"111",b"001",b"111",b"001",b"111",others=>"000");
signal memory : imem := (b"010",b"001",b"010",b"000",b"011",b"001",b"011",b"000",b"110",b"011",b"111",b"011",b"110",b"011",b"101",b"111",others=>"000");
begin
-- Process clk_read
-- clk_read : process (clk) -- runs only, when clk changed