Commit Graph

79 Commits

Author SHA1 Message Date
Yannick Reiß f357cd51bf Init leds with a definitive state 2025-03-16 17:28:17 +01:00
Yannick Reiß b5dad1b5e6 Merge pull request 'Implement atomic assembler' (#1) from atomic_assembly into master
Reviewed-on: https://git.nickr.eu/yannickreiss/brainfuck_processor/pulls/1
2024-05-24 17:12:36 +02:00
Yannick Reiß d43f79500d Implement atomic assembler 2024-05-24 17:07:32 +02:00
Yannick Reiß 595ae8ce20 Update readme and repositories 2024-05-17 12:03:16 +02:00
Yannick Reiß bbdf5ece5c
Copy FPGA design for use in TinyTapeout 2023-10-27 13:24:45 +02:00
Yannick Reiß 78077c7b13
Fix unplanned unnesting bug 2023-10-21 01:04:44 +02:00
Yannick Reiß 02136bd0b9
Change name of main file 2023-10-21 00:39:21 +02:00
Yannick Reiß 5d5b4d93d7
BUG: Token array now terminated by \0 2023-10-21 00:36:12 +02:00
Yannick Reiß 075cfddcaf
Create LICENSE 2023-10-17 21:15:22 +02:00
Yannick Reiß 5f45cbbb4f
Remove Vivado files 2023-10-05 22:01:12 +02:00
Yannick Reiß b21949e38f
Remove Vivado files 2023-10-05 15:44:59 +02:00
Yannick Reiß 8d340be824
Presentable program 2023-10-05 15:43:55 +02:00
schnick 799b79a899 Merge branch 'compiler' into 'master'
Compiler

See merge request schnick/bfpu!5
2023-10-05 13:04:51 +00:00
Yannick Reiß ddabe769b0
Example program 2023-10-05 15:02:40 +02:00
Yannick Reiß bbd5a5efda
Implement FPGA as target device into compiler 2023-10-05 14:20:10 +02:00
Yannick Reiß a4d8ea1374
FPGA is new default device, fuck bf to c compiling 2023-10-05 12:52:39 +02:00
Yannick Reiß 5b3c9a61be
Add repo location to README 2023-10-05 12:48:25 +02:00
schnick 63450af6ab Merge branch 'documentation' into 'master'
README.md

See merge request schnick/bfpu!4
2023-10-05 10:34:30 +00:00
schnick f05c1a9ae3 Merge branch 'fpga' into 'master'
Fpga

See merge request schnick/bfpu!3
2023-10-05 10:32:02 +00:00
Yannick Reiß 041a3e8113
Removed simulation duration to save time. 2023-10-05 12:30:40 +02:00
schnick ae5879cc71 Merge branch 'compiler' into 'master'
Compiler

See merge request schnick/bfpu!2
2023-10-05 10:26:47 +00:00
Yannick Reiß 8ab9e660c4
mplement README.md 2023-10-05 12:22:50 +02:00
Yannick Reiß e27c8a4505
Change instructions and testbench to test nested loops 2023-10-05 11:01:35 +02:00
Yannick Reiß 73d1db32c7
Change duration of testbench 2023-10-05 11:01:12 +02:00
Yannick Reiß ba0c56bc5f
Abstract Art due to f*** ups 2023-10-05 08:49:41 +02:00
Yannick Reiß a39b94c26f
Fix jumping bug 2023-10-05 08:49:21 +02:00
Yannick Reiß b530f66702
Implement state machine, arith and I/O instructions now working. 2023-10-04 19:32:13 +02:00
Yannick Reiß 65c6f85bb9
Implement testbench for bfpu 2023-10-04 15:46:23 +02:00
Yannick Reiß a7d7f30dad
Images of the schematic after each step 2023-10-04 12:12:03 +02:00
schnick 53cb4e7f92 Merge branch 'fpga' into 'master'
Fpga

See merge request schnick/bfpu!1
2023-10-04 09:29:57 +00:00
Yannick Reiß 1b4f753c54
First working implementation 2023-10-04 11:27:25 +02:00
Yannick Reiß 66a409c33e
Init TinyTapeout repository 2023-10-04 11:03:41 +02:00
Yannick Reiß 8da2a2b27e
Addition to proof of correctness 2023-10-04 10:06:58 +02:00
Yannick Reiß f906a6e4a3
Implement push and pop in branch 2023-09-27 20:44:03 +02:00
Yannick Reiß 30559c81a9
Implementation of branch, excluding stack 2023-09-26 20:42:36 +02:00
Yannick Reiß 180caa0b3c
Implement program memory 2023-09-26 14:14:18 +02:00
Yannick Reiß d27378e58f
Implement cell memory 2023-09-26 12:03:53 +02:00
Yannick Reiß 51fe976188
Rushed implementation connecting parts 2023-09-26 11:37:47 +02:00
Yannick Reiß bccd638d2b
Implement brainfuck ptr 2023-09-26 11:37:27 +02:00
Yannick Reiß 74c4ea39b5
No need for decoder 2023-09-26 11:37:06 +02:00
Yannick Reiß 090cd8c07a
Implement instruction memory 2023-09-26 11:36:50 +02:00
Yannick Reiß 75e722b222
Implement ALU 2023-09-26 11:34:53 +02:00
Yannick Reiß a94cf440c1
Add constraints for stage 1 2023-09-26 11:34:40 +02:00
Yannick Reiß ba7f2d8394
Prevent null arguments through command line 2023-09-26 07:33:09 +02:00
Yannick Reiß a8d8a4171a
Add constraints file 2023-09-26 07:27:03 +02:00
Yannick Reiß b02be01de1
Add files for fpga 2023-09-26 07:26:17 +02:00
Yannick Reiß 61baa3ebfc
Proof 2023-09-24 08:51:16 +02:00
Yannick Reiß e0c7116486
Proof of memory safety in main function. 2023-09-23 16:10:26 +02:00
Yannick Reiß 09183f43e1
minor changes for memory safety. 2023-09-23 16:10:01 +02:00
Yannick Reiß a2c746f57d
Add gitignore file 2023-09-22 15:22:16 +02:00