Update Verilog snippets

UltiSnips/verilog.snippets

@@ -42,3 +42,15 @@ endsnippet
 snippet ,double "set bus to size of a double word" A
 [63:0]$0
 endsnippet
+
+snippet begin "begin - end" iA
+begin
+	$1
+end
+$0
+endsnippet
+
+snippet def "Definition/Constant" b
+\`define ${1:NAME} ${2:VALUE}
+$0
+endsnippet

spell/de.utf-8.add

@@ -0,0 +1,2 @@
+transgender
+python

spell/en.utf-8.add

@@ -0,0 +1 @@
+t0