From 583d6f97902be8224bb5cc3d8aad5749d7289164 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Sat, 26 Aug 2023 08:21:47 +0200 Subject: [PATCH] Update Verilog snippets --- UltiSnips/verilog.snippets | 12 ++++++++++++ spell/de.utf-8.add | 2 ++ spell/de.utf-8.add.spl | Bin 0 -> 62 bytes spell/en.utf-8.add | 1 + spell/en.utf-8.add.spl | Bin 0 -> 29 bytes 5 files changed, 15 insertions(+) create mode 100644 spell/de.utf-8.add create mode 100644 spell/de.utf-8.add.spl create mode 100644 spell/en.utf-8.add create mode 100644 spell/en.utf-8.add.spl diff --git a/UltiSnips/verilog.snippets b/UltiSnips/verilog.snippets index 677fd39..e7751a8 100644 --- a/UltiSnips/verilog.snippets +++ b/UltiSnips/verilog.snippets @@ -42,3 +42,15 @@ endsnippet snippet ,double "set bus to size of a double word" A [63:0]$0 endsnippet + +snippet begin "begin - end" iA +begin + $1 +end +$0 +endsnippet + +snippet def "Definition/Constant" b +\`define ${1:NAME} ${2:VALUE} +$0 +endsnippet diff --git a/spell/de.utf-8.add b/spell/de.utf-8.add new file mode 100644 index 0000000..1316625 --- /dev/null +++ b/spell/de.utf-8.add @@ -0,0 +1,2 @@ +transgender +python diff --git a/spell/de.utf-8.add.spl b/spell/de.utf-8.add.spl new file mode 100644 index 0000000000000000000000000000000000000000..85b36cbb8c668bbc92964d581d01d8966fbaa027 GIT binary patch literal 62 zcmWIZ^erw(&B-zP&%nT-%v4aqSjkwzn8BFOn8(P#Sj3nJq>CBT8B>9D3Xo)EVBjqR HDun<5+9wOZ literal 0 HcmV?d00001 diff --git a/spell/en.utf-8.add b/spell/en.utf-8.add new file mode 100644 index 0000000..e9c37cf --- /dev/null +++ b/spell/en.utf-8.add @@ -0,0 +1 @@ +t0 diff --git a/spell/en.utf-8.add.spl b/spell/en.utf-8.add.spl new file mode 100644 index 0000000000000000000000000000000000000000..441fcb04414bcbc8f1a8030ab5620747ae3b97c7 GIT binary patch literal 29 dcmWIZ^erw(&B-zP&%nUI##q8=zzAeO0RV0-1nU3* literal 0 HcmV?d00001