Register

Makefile

@@ -1,7 +1,7 @@
 CHDL	=	ghdl
 FLAGS	=	--std=08
 STOP	=	60000ns
-PARTS	=	alu
+PARTS	=	alu stack
 
 all: $(PARTS)
 
@@ -15,4 +15,4 @@ clean:
 	find . -name '*.cf' -exec rm -r {} \;
 	find . -name '*.ghw' -exec rm -r {} \;
 	find . -name '*.entity' -exec rm -r {} \;
-	find . -name $(PARTS)_tb -exec rm -r {} \;
+	find . -name '*_tb' -exec rm -r {} \;

regs.vhd

@@ -0,0 +1,41 @@
+-- regs.vhd
+-- Date:   Mon Mar  4 16:49:33 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity regs is
+  port map(
+    clk          : in  std_logic;
+    write_enable : in  std_logic;
+    value_write  : in  std_logic_vector(7 downto 0);
+    register1    : in  std_logic_vector(2 downto 0);
+    register2    : in  std_logic_vector(2 downto 0);
+    value_r1     : out std_logic_vector(7 downto 0);
+    value_r2     : out std_logic_vector(7 downto 0)
+    );
+end regs;
+
+architecture Implementation of regs is
+  type regbench is array(0 to 7) of std_logic_vector(7 downto 0);
+
+  signal registerblock : regbench := (others => (others => '0'));
+begin
+
+  -- react only on clock changes
+  process (clk)                         -- runs only, when clk changed
+  begin
+    if rising_edge(clk) then
+      -- check if write is enabled
+      if to_integer(unsigned(write_enable)) = 1 then
+        -- write data_in to wr_idx
+        registerblock(to_integer(unsigned(register1))) <= value_write;
+      end if;
+    end if;
+  end process;
+
+  value_r1 <= registerblock(to_integer(unsigned(register1)));
+  value_r2 <= registerblock(to_integer(unsigned(register2)));
+end Implementation;

tb_alu.vhdl

@@ -59,7 +59,7 @@ begin
     target      <= operand1 xor "11111111";
     wait for 5 ns;
     if not (target = result) then
-      write(lineBuffer, string'("Error on Not"));
+      write(lineBuffer, string'("=> Error on Not"));
       writeline(output, lineBuffer);
     end if;
 
@@ -69,7 +69,7 @@ begin
     target   <= "00000000";
     wait for 5 ns;
     if not (unsigned(result) = unsigned(target)) then
-      write(lineBuffer, string'("Error on Parity"));
+      write(lineBuffer, string'("=> Error on Parity"));
       writeline(output, lineBuffer);
     end if;
 
@@ -79,7 +79,7 @@ begin
     target   <= "00000010";
     wait for 5 ns;
     if not (unsigned(result) = 1) then
-      write(lineBuffer, string'("Error on Count"));
+      write(lineBuffer, string'("=> Error on Count"));
       writeline(output, lineBuffer);
     end if;
 
@@ -89,7 +89,7 @@ begin
     target   <= operand1 and operand2;
     wait for 5 ns;
     if not (result = target) then
-      write(lineBuffer, string'("Error on And"));
+      write(lineBuffer, string'("=> Error on And"));
       writeline(output, lineBuffer);
     end if;
 
@@ -98,7 +98,7 @@ begin
     operator <= "010001";
     wait for 5 ns;
     if not (result = (operand1 or operand2)) then
-      write(lineBuffer, string'("Error on Or"));
+      write(lineBuffer, string'("=> Error on Or"));
       writeline(output, lineBuffer);
     end if;
 
@@ -107,7 +107,7 @@ begin
     operator <= "010101";
     wait for 5 ns;
     if not (result = (operand1 xor operand2)) then
-      write(lineBuffer, string'("Error on Xor"));
+      write(lineBuffer, string'("=> Error on Xor"));
       writeline(output, lineBuffer);
     end if;
 
@@ -116,7 +116,7 @@ begin
     operator <= "011001";
     wait for 5 ns;
     if not (result = operand2) then
-      write(lineBuffer, string'("Error on Move"));
+      write(lineBuffer, string'("=> Error on Move"));
       writeline(output, lineBuffer);
     end if;
 
@@ -125,7 +125,7 @@ begin
     operator <= "011101";
     wait for 5 ns;
     if not (result = std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2))))) then
-      write(lineBuffer, string'("Error on Shift left"));
+      write(lineBuffer, string'("=> Error on Shift left"));
       writeline(output, lineBuffer);
     end if;
 
@@ -134,7 +134,7 @@ begin
     operator <= "100001";
     wait for 5 ns;
     if not (result = std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2))))) then
-      write(lineBuffer, string'("Error on Shift right"));
+      write(lineBuffer, string'("=> Error on Shift right"));
       writeline(output, lineBuffer);
     end if;
 
@@ -143,7 +143,7 @@ begin
     operator <= "000010";
     wait for 5 ns;
     if not (result = std_logic_vector(unsigned(operand1) + unsigned(operand2))) then
-      write(lineBuffer, string'("Error on Add"));
+      write(lineBuffer, string'("=> Error on Add"));
       writeline(output, lineBuffer);
     end if;
 
@@ -152,7 +152,7 @@ begin
     operator <= "000110";
     wait for 5 ns;
     if not (result = std_logic_vector(signed(operand1) - signed(operand2))) then
-      write(lineBuffer, string'("Error on Sub"));
+      write(lineBuffer, string'("=> Error on Sub"));
       writeline(output, lineBuffer);
     end if;
 
@@ -161,7 +161,7 @@ begin
     operator <= "000011";
     wait for 5 ns;
     if not (result = "00000000") then
-      write(lineBuffer, string'("Error on Set if Equal"));
+      write(lineBuffer, string'("=> Error on Set if Equal"));
       writeline(output, lineBuffer);
     end if;
 
@@ -170,7 +170,7 @@ begin
     operator <= "000111";
     wait for 5 ns;
     if not (result = "00000001") then
-      write(lineBuffer, string'("Error on Set if Lower"));
+      write(lineBuffer, string'("=> Error on Set if Lower"));
       writeline(output, lineBuffer);
     end if;
 
@@ -179,7 +179,7 @@ begin
     operator <= "001011";
     wait for 5 ns;
     if not (result = "00000001") then
-      write(lineBuffer, string'("Error on Set if lower unsigned"));
+      write(lineBuffer, string'("=> Error on Set if lower unsigned"));
       writeline(output, lineBuffer);
     end if;
 

tb_regs.vhdl

@@ -0,0 +1,49 @@
+-- tb_regs.vhdl
+-- Date:   Mon Mar  4 17:58:35 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+
+library std;
+use std.textio.all;
+
+entity regs_tb is
+end regs_tb;
+
+architecture testing of regs_tb is
+  signal clk          : std_logic;
+  constant clk_period : time := 10 ns;
+
+  -- Inputs
+  signal write_enable : std_logic;
+  signal value_write  : std_logic_vector(7 downto 0);
+  signal register1    : std_logic_vector(2 downto 0);
+  signal register2    : std_logic_vector(2 downto 0);
+  signal value_r1     : std_logic_vector(7 downto 0);
+  signal value_r2     : std_logic_vector(7 downto 0);
+
+begin
+
+  uut : entity work.regs(Implementation)
+    port map(
+      clk          => clk,
+      write_enable => write_enable,
+      value_write  => value_write,
+      register1    => register1,
+      register2    => register2,
+      value_r1     => value_r1,
+      value_r2     => value_r2
+      );
+
+  clk_process : process                 -- runs always
+  begin
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process;
+end testing;