Register

regs.vhd

@@ -0,0 +1,41 @@
+-- regs.vhd
+-- Date:   Mon Mar  4 16:49:33 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity regs is
+  port map(
+    clk          : in  std_logic;
+    write_enable : in  std_logic;
+    value_write  : in  std_logic_vector(7 downto 0);
+    register1    : in  std_logic_vector(2 downto 0);
+    register2    : in  std_logic_vector(2 downto 0);
+    value_r1     : out std_logic_vector(7 downto 0);
+    value_r2     : out std_logic_vector(7 downto 0)
+    );
+end regs;
+
+architecture Implementation of regs is
+  type regbench is array(0 to 7) of std_logic_vector(7 downto 0);
+
+  signal registerblock : regbench := (others => (others => '0'));
+begin
+
+  -- react only on clock changes
+  process (clk)                         -- runs only, when clk changed
+  begin
+    if rising_edge(clk) then
+      -- check if write is enabled
+      if to_integer(unsigned(write_enable)) = 1 then
+        -- write data_in to wr_idx
+        registerblock(to_integer(unsigned(register1))) <= value_write;
+      end if;
+    end if;
+  end process;
+
+  value_r1 <= registerblock(to_integer(unsigned(register1)));
+  value_r2 <= registerblock(to_integer(unsigned(register2)));
+end Implementation;

tb_regs.vhdl

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+-- tb_regs.vhdl
+-- Date:   Mon Mar  4 17:58:35 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    yannick.reiss@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+
+library std;
+use std.textio.all;
+
+entity regs_tb is
+end regs_tb;
+
+architecture testing of regs_tb is
+  signal clk          : std_logic;
+  constant clk_period : time := 10 ns;
+
+  -- Inputs
+  signal write_enable : std_logic;
+  signal value_write  : std_logic_vector(7 downto 0);
+  signal register1    : std_logic_vector(2 downto 0);
+  signal register2    : std_logic_vector(2 downto 0);
+  signal value_r1     : std_logic_vector(7 downto 0);
+  signal value_r2     : std_logic_vector(7 downto 0);
+
+begin
+
+  uut : entity work.regs(Implementation)
+    port map(
+      clk          => clk,
+      write_enable => write_enable,
+      value_write  => value_write,
+      register1    => register1,
+      register2    => register2,
+      value_r1     => value_r1,
+      value_r2     => value_r2
+      );
+
+  clk_process : process                 -- runs always
+  begin
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process;
+end testing;