nvim/UltiSnips/verilog.snippets

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snippet reg_ "Register of size." iA
reg [${1:7}:${2:0}] ${3:register};$0
endsnippet
snippet wire_ "Wire as bus" iA
wire [${1:7}:${2:0}] ${3:wire};$0
endsnippet
global !p
def complete(t, opts):
if t:
opts = [ m[len(t):] for m in opts if m.startswith(t) ]
if len(opts) == 1:
return opts[0]
return "(" + "|".join(opts) + ")"
endglobal
snippet always "Do something always @" b
always @($1`!p snip.rv=complete(t[1], ['*', 'posedge clk', 'negedge clk', 'posedge rst_n', 'negedge rst_n'])`) begin
$2
end$0
endsnippet
snippet al "Do something always @" b
always @($1) begin
$2
end$0
endsnippet
snippet ,byte "set bus to size of a byte" A
[7:0]$0
endsnippet
snippet ,half "set bus to size of half word" A
[15:0]$0
endsnippet
snippet ,word "set bus to size of a word" A
[31:0]$0
endsnippet
snippet ,double "set bus to size of a double word" A
[63:0]$0
endsnippet
snippet module "Add module declaration" b
module ${1:MODULE_NAME} (
$2
);
$0
endmodule // $1
snippet begin "begin - end" iA
begin
$1
end
$0
endsnippet
snippet def "Definition/Constant" b
\`define ${1:NAME} ${2:VALUE}
$0
endsnippet
snippet filename "Get Filename" b
// `pwd`/`!p snip.rv = fn`
endsnippet