new snippet

UltiSnips/verilog.snippets

@@ -1,7 +1,11 @@
-snippet "reg []" "Register of size." A
+snippet reg_ "Register of size." iA
 reg [${1:7}:${2:0}] ${3:register};$0
 endsnippet
 
+snippet wire_ "Wire as bus" iA
+wire [${1:7}:${2:0}] ${3:wire};$0
+endsnippet
+
 global !p
 def complete(t, opts):
 	if t:
@@ -14,12 +18,11 @@ endglobal
 snippet always "Do something always @" b
 always @($1`!p snip.rv=complete(t[1], ['*', 'posedge clk', 'negedge clk', 'posedge rst_n', 'negedge rst_n'])`) begin
 	$2
-end $0
+end$0
 endsnippet
 
 snippet al "Do something always @" b
 always @($1) begin
 	$2
-end $0
+end$0
 endsnippet
-