 Yannick Reiß
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721b1fb5c6
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Testbenches
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2024-02-04 12:08:07 +01:00 |
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a519e55f5b
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Add Cpu16 bitstraem
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2024-02-01 09:16:47 +01:00 |
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3bc4b6855e
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Add example PMem, Connect constraints
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2024-02-01 09:11:45 +01:00 |
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fd8b4f9f85
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Add constraints
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2024-02-01 09:11:13 +01:00 |
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3e8a72fa05
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Add unconditional jump expressions
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2024-02-01 08:01:24 +01:00 |
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d27dee2745
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Jump only if branch acknowledges
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2024-02-01 07:49:29 +01:00 |
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8c4286cd90
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Always using 32 bit instructions, Implement enable handler
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2024-02-01 07:47:21 +01:00 |
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d57ca49821
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Implement and connect branch
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2024-02-01 06:58:12 +01:00 |
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8f14afc6ec
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Removed Bus access from RAM
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2024-01-31 17:39:33 +01:00 |
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Yannick Reiß
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fafd9320af
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Connecting I2C
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2024-01-31 15:20:17 +01:00 |
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Yannick Reiß
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4385bc6dcc
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Forgot signal keywords
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2024-01-31 14:54:08 +01:00 |
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Yannick Reiß
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18010b4821
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Implement clock splitter for I2C
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2024-01-31 14:52:46 +01:00 |
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Yannick Reiß
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f8076f66cb
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Fix loop assignment
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2024-01-31 13:18:15 +01:00 |
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Yannick Reiß
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34bc6162ed
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Not driving multiple ports now
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2024-01-31 13:16:09 +01:00 |
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Yannick Reiß
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c1ddd00634
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Add I2C Entity
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2024-01-31 13:12:34 +01:00 |
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Yannick Reiß
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c5853fc280
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Add I2C to RAM
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2024-01-31 12:47:15 +01:00 |
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Yannick Reiß
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9505af3467
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RISCV V1
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2024-01-30 21:50:57 +01:00 |
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Yannick Reiß
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683ac9a8d4
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init
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2024-01-30 09:42:06 +01:00 |