Testbenches

tb/tb_alu.vhd

@@ -0,0 +1,121 @@
+-- tb_alu.vhd
+-- Date:   Wed Jan 31 11:39:58 2024
+-- Author:    Yannick Reiß
+-- E-Mail:    schnick@nickr.eu
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity tb_alu is
+end tb_alu;
+
+architecture Testbench of tb_alu is
+  signal alu_op : std_logic_vector(3 downto 0);
+  signal input1 : std_logic_vector(15 downto 0);
+  signal input2 : std_logic_vector(15 downto 0);
+  signal result : std_logic_vector(15 downto 0);
+
+  -- Helper procedure to print error message
+  procedure print_error(msg : string) is
+  begin
+    report "Error: " & msg;
+  end procedure;
+
+  -- Helper procedure to check if the result is as expected
+  procedure check_result(expected : std_logic_vector) is
+  begin
+    if result /= expected then
+      print_error("Unexpected result. Expected: " & to_string(expected) & " Got: " & to_string(result));
+    end if;
+  end procedure;
+
+begin
+
+  uut : entity work.Alu(Implementation)
+    port map(
+      alu_op => alu_op,
+      input1 => input1,
+      input2 => input2,
+      result => result
+      );
+
+  Trigger : process
+  begin
+
+    -- Test ADD operation
+    alu_op <= "0000";
+    input1 <= "0000000000000000";
+    input2 <= "0000000000000000";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000000");
+
+    -- Test SUB operation
+    alu_op <= "0010";
+    input1 <= "0000000000000100";
+    input2 <= "0000000000000001";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000011");
+
+    -- Test SLL operation
+    alu_op <= "0011";
+    input1 <= "0000000000000001";
+    input2 <= "0000000000000010";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000100");
+
+    -- Test SLT operation
+    alu_op <= "0100";
+    input1 <= "0000000000000001";
+    input2 <= "0000000000000010";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000000");
+
+    -- Test SLTU operation
+    alu_op <= "0101";
+    input1 <= "0000000000000010";
+    input2 <= "0000000000000001";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000001");
+
+    -- Test XOR operation
+    alu_op <= "0110";
+    input1 <= "0000000000001010";
+    input2 <= "0000000000001100";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000110");
+
+    -- Test SRL operation
+    alu_op <= "0111";
+    input1 <= "0000000000001100";
+    input2 <= "0000000000000001";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000110");
+
+    -- Test SRA operation
+    alu_op <= "1000";
+    input1 <= "0000000000001111";
+    input2 <= "0000000000000001";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000001111");
+
+    -- Test OR operation
+    alu_op <= "1010";
+    input1 <= "0000000000001010";
+    input2 <= "0000000000000101";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000001111");
+
+    -- Test AND operation
+    alu_op <= "1011";
+    input1 <= "0000000000001010";
+    input2 <= "0000000000000101";
+    wait for 1 ns;                      -- Allow for processing
+    check_result("0000000000000000");
+
+    -- Print test successful if no errors occurred
+    report "Test successful";
+
+    wait;
+  end process Trigger;
+end Testbench;
+