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Copy FPGA design for use in TinyTapeout

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This commit is contained in:
yannickreiss
2023-10-27 13:24:45 +02:00
parent 78077c7b13
commit bbdf5ece5c
13 changed files with 1360 additions and 190 deletions
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87
TinyTapeout/src/alu.vhd Normal file
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-- alu.vhd
-- Created on: Di 26. Sep 10:07:59 CEST 2023
-- Author(s): Yannick Reiß
-- Content: Decode instructions and control brainfuck logic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity alu: alu crtl
entity alu is
port(
instruction : in std_logic_vector(2 downto 0);
old_cell : in std_logic_vector(7 downto 0);
old_pointer : in std_logic_vector(15 downto 0);
extern_in : in std_logic_vector(7 downto 0);
new_cell : out std_logic_vector(7 downto 0);
new_pointer : out std_logic_vector(15 downto 0);
enable_cell : out std_logic;
enable_ptr : out std_logic;
extern_out : out std_logic_vector(7 downto 0)
);
end alu;
-- Architecture implementation of alu: implements table
architecture implementation of alu is
signal buffer_out : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Process p_instruction
p_instruction : process (extern_in, instruction, old_cell, old_pointer)
begin
case instruction is
when "000" =>
enable_cell <= '0';
enable_ptr <= '1';
new_pointer <= std_logic_vector(unsigned(old_pointer) + 1);
new_cell <= old_cell;
-- buffer_out <= "00000000";
when "001" =>
enable_cell <= '0';
enable_ptr <= '1';
new_pointer <= std_logic_vector(unsigned(old_pointer) - 1);
new_cell <= old_cell;
-- buffer_out <= "00000000";
when "010" =>
enable_cell <= '1';
enable_ptr <= '0';
new_cell <= std_logic_vector(unsigned(old_cell) + 1);
new_pointer <= old_pointer;
-- buffer_out <= "00000000";
when "011" =>
enable_cell <= '1';
enable_ptr <= '0';
new_cell <= std_logic_vector(unsigned(old_cell) - 1);
new_pointer <= old_pointer;
-- buffer_out <= "00000000";
when "100" =>
enable_cell <= '1';
enable_ptr <= '0';
new_cell <= extern_in;
new_pointer <= old_pointer;
-- buffer_out <= "00000000";
when "101" =>
enable_cell <= '0';
enable_ptr <= '0';
buffer_out <= old_cell;
new_pointer <= old_pointer;
new_cell <= old_cell;
when others =>
enable_cell <= '0';
enable_ptr <= '0';
new_pointer <= old_pointer;
new_cell <= old_cell;
-- buffer_out <= "00000000";
end case;
end process;
extern_out <= buffer_out;
end implementation;

12
TinyTapeout/src/bfpu.v
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module tt_um_yannickreiss_bfpu(input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable path (active high: 0 = input, 1 = output
input wire ena,
input wire clk,
input wire rst_n);
endmodule

202
TinyTapeout/src/bfpu.vhd Normal file
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-- bfpu.vhd
-- Created on: Di 26. Sep 08:27:47 CEST 2023
-- Author(s): Yannick Reiß
-- Content: Connect the entities of the processing unit.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity bfpu: brainfuck processing unit
entity bfpu is
port(
clk : in std_logic; -- board clock
sw : in std_logic_vector(7 downto 0); -- Input for instruction ,
debug : out std_logic_vector(7 downto 0); -- Value of currently selected logic cell.
led : out std_logic_vector(7 downto 0) -- Output for instruction .
);
end bfpu;
-- Architecture arch of bfpu: setup and connect components
architecture arch of bfpu is
component instructionMemory
port(
instructionAddr : in std_logic_vector(7 downto 0);
instruction : out std_logic_vector(2 downto 0)
);
end component;
component alu
port(
instruction : in std_logic_vector(2 downto 0);
old_cell : in std_logic_vector(7 downto 0);
old_pointer : in std_logic_vector(15 downto 0);
extern_in : in std_logic_vector(7 downto 0);
new_cell : out std_logic_vector(7 downto 0);
new_pointer : out std_logic_vector(15 downto 0);
enable_cell : out std_logic;
enable_ptr : out std_logic;
extern_out : out std_logic_vector(7 downto 0)
);
end component;
component ptr
port(
clk : in std_logic;
enable_ptr : in std_logic;
new_ptr : in std_logic_vector(15 downto 0);
old_ptr : out std_logic_vector(15 downto 0)
);
end component;
component cellblock
port(
clk : in std_logic;
enable : in std_logic;
address : in std_logic_vector(15 downto 0);
new_cell : in std_logic_vector(7 downto 0);
old_cell : out std_logic_vector(7 downto 0)
);
end component;
component program_counter
port(
clk : in std_logic;
enable : in std_logic;
jmp : in std_logic;
pc_in : in std_logic_vector(7 downto 0);
pc_out : out std_logic_vector(7 downto 0)
);
end component;
component branch
port(
clk : in std_logic;
state : in std_logic;
instruction : in std_logic_vector(2 downto 0);
instr_addr : in std_logic_vector(7 downto 0);
cell_value : in std_logic_vector(7 downto 0);
skip : out std_logic;
jump : out std_logic;
pc_enable : out std_logic;
pc_out : out std_logic_vector(7 downto 0)
);
end component;
signal s_clk : std_logic;
signal s_in : std_logic_vector(7 downto 0) := (others => '0');
signal s_out : std_logic_vector(7 downto 0) := (others => '0');
signal s_instrAddr : std_logic_vector(7 downto 0) := "00000000";
signal s_instruction : std_logic_vector(2 downto 0) := "000";
signal s_cell_out : std_logic_vector(7 downto 0) := (others => '0');
signal s_cell_in : std_logic_vector(7 downto 0) := (others => '0');
signal s_ptr_out : std_logic_vector(15 downto 0) := (others => '0');
signal s_ptr_in : std_logic_vector(15 downto 0) := (others => '0');
signal s_enable_cells : std_logic := '0';
signal s_enable_ptr : std_logic := '0';
signal s_enable_pc : std_logic := '1';
signal s_jmp_pc : std_logic := '0';
signal s_jmp_addr_pc : std_logic_vector(7 downto 0) := "00000000";
signal s_skip : std_logic := '0';
signal s_enable_cells_o : std_logic := '0';
signal s_enable_ptr_o : std_logic := '0';
signal processor_state : std_logic := '0'; -- 0: execute; 1: write back
begin
-- clock and state logic
s_clk <= clk;
-- Process state change state between execute and write back
state : process (s_clk) -- runs only, when s_clk changed
begin
if rising_edge(s_clk) then
processor_state <= not processor_state;
end if;
end process;
-- Process in_out set in- and output on clk high and exec/write back
in_out : process (s_clk) -- runs only, when s_clk changed
begin
if rising_edge(s_clk) then
if processor_state = '1' then
led <= s_out;
else
s_in <= sw;
end if;
end if;
end process;
instrMemory : instructionMemory
port map(
instructionAddr => s_instrAddr,
instruction => s_instruction
);
alu_entity : alu
port map(
instruction => s_instruction,
old_cell => s_cell_out,
old_pointer => s_ptr_out,
extern_in => s_in,
new_cell => s_cell_in,
new_pointer => s_ptr_in,
enable_cell => s_enable_cells_o,
enable_ptr => s_enable_ptr_o,
extern_out => s_out
);
ptr_bf : ptr
port map(
clk => s_clk,
enable_ptr => s_enable_ptr,
new_ptr => s_ptr_in,
old_ptr => s_ptr_out
);
cellblock_bf : cellblock
port map(
clk => s_clk,
enable => s_enable_cells,
address => s_ptr_out,
new_cell => s_cell_in,
old_cell => s_cell_out
);
pc : program_counter
port map(
clk => s_clk,
enable => s_enable_pc and processor_state,
jmp => s_jmp_pc,
pc_in => s_jmp_addr_pc,
pc_out => s_instrAddr
);
branch_bf : branch
port map(
clk => s_clk,
state => processor_state,
instruction => s_instruction,
instr_addr => s_instrAddr,
cell_value => s_cell_out,
skip => s_skip,
jump => s_jmp_pc,
pc_enable => s_enable_pc,
pc_out => s_jmp_addr_pc
);
s_enable_ptr <= not s_skip and s_enable_ptr_o and processor_state;
s_enable_cells <= not s_skip and s_enable_cells_o and processor_state;
debug <= s_cell_out;
end arch;

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TinyTapeout/src/branch.vhd Normal file
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-- branch.vhd
-- Created on: Di 26. Sep 13:47:51 CEST 2023
-- Author(s): Yannick Reiss <yannick.reiss@protonmail.ch>
-- Content: Branch unit / ALU for program counter XD
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- TODO: CHECK PUSH AND POP AND THE PHASES/STATES OF PC_ENABLE
-- Entity branch: branch
entity branch is
port(
clk : in std_logic;
state : in std_logic;
instruction : in std_logic_vector(2 downto 0);
instr_addr : in std_logic_vector(7 downto 0);
cell_value : in std_logic_vector(7 downto 0);
skip : out std_logic;
pc_enable : out std_logic;
jump : out std_logic;
pc_out : out std_logic_vector(7 downto 0)
);
end branch;
-- Architecture impl of branch:
architecture impl of branch is
type stack is array(0 to 255) of std_logic_vector(7 downto 0);
signal addr_stack : stack := (others => (others => '0'));
signal nested : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops
signal skip_internal : std_logic := '0';
signal stack_ptr : std_logic_vector(7 downto 0) := (others => '0');
signal pc_enable_internal : std_logic := '1';
begin
-- Process branch_compute Thing that does things.
branch_compute : process (all) -- runs only, when all changed
begin
if rising_edge(clk) then
-- set addr_stack
if skip = '0' then
-- pop part 1
-- push part 2
if state = '1' and instruction = "110" then
addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr;
end if;
end if;
-- set nested
if state = '0' and skip_internal = '1' then
-- deeper nest
if instruction = "110" then
nested <= std_logic_vector(unsigned(nested) + 1);
end if;
end if;
if state = '1' and skip_internal = '1' then
-- nested loop ended
if instruction = "111" then
nested <= std_logic_vector(unsigned(nested) - 1);
end if;
end if;
-- set skip
-- on instruction [
if instruction = "110" and state = '0' then
if unsigned(cell_value) > 0 and not ( skip_internal = '1' or unsigned(nested) > 0 ) then
skip_internal <= '0';
else
skip_internal <= '1';
end if;
end if;
-- on instruction ]
if state = '0' and instruction = "111" then
if skip_internal = '1' and unsigned(nested) > 0 then
skip_internal <= '1';
else
skip_internal <= '0';
end if;
end if;
-- set stack_ptr
if skip_internal = '0' then
-- pop part 2
if state = '1' and instruction = "111" then
stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1);
end if;
-- push part 1
if state = '0' and instruction = "110" then
stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1);
end if;
end if;
-- set pc_enable
pc_enable_internal <= not state;
-- set jump
if instruction = "111" and skip = '0' and state = '0' then
jump <= '1';
else
jump <= '0';
end if;
end if;
end process;
-- connect signals to pins
skip <= skip_internal;
pc_enable <= pc_enable_internal;
pc_out <= addr_stack(to_integer(unsigned(stack_ptr)));
end impl;

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TinyTapeout/src/cellMemory.vhd Normal file
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-- cellMemory.vhd
-- Created on: Di 26. Sep 11:39:10 CEST 2023
-- Author(s): Yannick Reiß
-- Content: Cell memory as part of brainfuck logic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity cellblock
entity cellblock is
port(
clk : in std_logic; -- clock with speed of board clock
enable : in std_logic;
address : in std_logic_vector(15 downto 0);
new_cell : in std_logic_vector(7 downto 0);
old_cell : out std_logic_vector(7 downto 0)
);
end cellblock;
-- Architecture arch of cellblock: read on every clock cycle to cell.
architecture arch of cellblock is
type empty is array(0 to 65535) of std_logic_vector(7 downto 0);
signal memory : empty := (others => (others => '0'));
begin
-- Process clk_read
clk_read : process (clk, enable) -- runs only, when clk changed
begin
if rising_edge(clk) and enable = '1' then
memory(to_integer(unsigned(address))) <= new_cell;
end if;
end process;
old_cell <= memory(to_integer(unsigned(address)));
end arch;

116
TinyTapeout/src/cells.v
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/*
This file provides the mapping from the Wokwi modules to Verilog HDL
It's only needed for Wokwi designs
*/
`define default_netname none
// custom cells
module reg_cell (input wire clk,
input wire d,
output wire q);
reg register;
always @(posedge clk) begin
register = d;
end
assign q = register;
endmodule // reg_cell
// TinyTapeout cells
module buffer_cell (
input wire in,
output wire out
);
assign out = in;
endmodule
module and_cell (
input wire a,
input wire b,
output wire out
);
assign out = a & b;
endmodule
module or_cell (
input wire a,
input wire b,
output wire out
);
assign out = a | b;
endmodule
module xor_cell (
input wire a,
input wire b,
output wire out
);
assign out = a ^ b;
endmodule
module nand_cell (
input wire a,
input wire b,
output wire out
);
assign out = !(a&b);
endmodule
module not_cell (
input wire in,
output wire out
);
assign out = !in;
endmodule
module mux_cell (
input wire a,
input wire b,
input wire sel,
output wire out
);
assign out = sel ? b : a;
endmodule
module dff_cell (
input wire clk,
input wire d,
output reg q,
output wire notq
);
assign notq = !q;
always @(posedge clk)
q <= d;
endmodule
module dffsr_cell (
input wire clk,
input wire d,
input wire s,
input wire r,
output reg q,
output wire notq
);
assign notq = !q;
always @(posedge clk or posedge s or posedge r) begin
if (r)
q <= 0;
else if (s)
q <= 1;
else
q <= d;
end
endmodule

62
TinyTapeout/src/config.tcl
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# PLEASE DO NOT EDIT THIS FILE!
# If you get stuck with this config, please open an issue or get in touch via the discord.
# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html
# User config
set script_dir [file dirname [file normalize [info script]]]
# read some user config that is written by the setup.py program.
# - the name of the module is defined
# - the list of source files
source $::env(DESIGN_DIR)/user_config.tcl
# save some time
set ::env(RUN_KLAYOUT_XOR) 0
set ::env(RUN_KLAYOUT_DRC) 0
# don't put clock buffers on the outputs
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
# allow use of specific sky130 cells
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
# reduce wasted space
set ::env(TOP_MARGIN_MULT) 1
set ::env(BOTTOM_MARGIN_MULT) 1
set ::env(LEFT_MARGIN_MULT) 6
set ::env(RIGHT_MARGIN_MULT) 6
# absolute die size
set ::env(FP_SIZING) absolute
set ::env(PL_BASIC_PLACEMENT) {0}
set ::env(GRT_ALLOW_CONGESTION) "1"
# otherwise fails on small designs at global placement
set ::env(GRT_CELL_PADDING) "4"
set ::env(FP_IO_HLENGTH) 2
set ::env(FP_IO_VLENGTH) 2
# use alternative efabless decap cells to solve LI density issue
set ::env(DECAP_CELL) "\
sky130_fd_sc_hd__decap_3 \
sky130_fd_sc_hd__decap_4 \
sky130_fd_sc_hd__decap_6 \
sky130_fd_sc_hd__decap_8 \
sky130_ef_sc_hd__decap_12"
# clock
set ::env(CLOCK_TREE_SYNTH) 1
# period is in ns, so 20ns == 50mHz
set ::env(CLOCK_PERIOD) "20"
set ::env(CLOCK_PORT) {clk}
# hold/slack margin
# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8
# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8
# don't use power rings or met5
set ::env(DESIGN_IS_CORE) 0
set ::env(RT_MAX_LAYER) {met4}

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TinyTapeout/src/instructionMemory.vhd Normal file
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-- instructionMemory.vhd
-- Created on: Di 26. Sep 07:43:20 CEST 2023
-- Author(s): Yannick Reiß
-- Content: Instruction memory; Read and write operations are controlled externally.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity instructionMemory: Currently ROM; TODO: Add write enable when implementing a bus.
entity instructionMemory is
port(
instructionAddr : in std_logic_vector(7 downto 0); -- We start with 256 instructions
instruction : out std_logic_vector(2 downto 0) -- instruction in current cell
);
end instructionMemory;
-- Architecture arch of instructionMemory: read on every clock cycle to instruction.
architecture arch of instructionMemory is
type imem is array(0 to 255) of std_logic_vector(2 downto 0);
signal memory : imem := (b"010",b"001",b"010",b"000",b"011",b"001",b"011",b"000",b"110",b"011",b"111",b"011",b"110",b"011",b"101",b"111",others=>"000");
begin
-- Process clk_read
-- clk_read : process (clk) -- runs only, when clk changed
-- begin
--
-- if rising_edge(clk) then
--
-- instruction <= memory(to_integer(unsigned(instructionAddr)));
--
-- end if;
-- end process;
instruction <= memory(to_integer(unsigned(instructionAddr)));
end arch;

35
TinyTapeout/src/memoryPointer.vhd Normal file
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-- memoryPointer.vhd
-- Created on: Di 26. Sep 11:11:49 CEST 2023
-- Author(s): Yannick Reiß
-- Content: Store current ptr. Part of brainfuck logic
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity ptr: 15 bit pointer to cell
entity ptr is
port(
clk : in std_logic;
enable_ptr : in std_logic;
new_ptr : in std_logic_vector(15 downto 0);
old_ptr : out std_logic_vector(15 downto 0)
);
end ptr;
-- Architecture implement_ptr of ptr:
architecture implement_ptr of ptr is
signal reg : std_logic_vector(15 downto 0) := (others => '0');
begin
-- Process Write set new_ptr
write : process (clk, enable_ptr) -- runs only, when clk changed
begin
if rising_edge(clk) and enable_ptr = '1' then
reg <= new_ptr;
end if;
end process;
old_ptr <= reg;
end implement_ptr;

40
TinyTapeout/src/programCounter.vhd Normal file
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-- programCounter.vhd
-- Created on: Di 26. Sep 12:45:10 CEST 2023
-- Author(s): Yannick Reiß
-- Content: Set and store program counter only. Logic entirely in branch!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Entity program_counter: set/store pc
entity program_counter is
port(
clk : in std_logic;
enable : in std_logic;
jmp : in std_logic;
pc_in : in std_logic_vector(7 downto 0);
pc_out : out std_logic_vector(7 downto 0)
);
end program_counter;
-- Architecture pc of program_counter:
architecture pc of program_counter is
signal pc_intern : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Process count
count : process (clk, enable, jmp) -- runs only, when clk, enable, jmp changed
begin
if rising_edge(clk) and enable = '1' then
if jmp = '1' then
pc_intern <= pc_in;
else
pc_intern <= std_logic_vector(unsigned(pc_intern) + 1);
end if;
end if;
end process;
pc_out <= pc_intern;
end pc;