From bbdf5ece5c9f3040163a5391d0b86e53092d7d06 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Fri, 27 Oct 2023 13:24:45 +0200 Subject: [PATCH] Copy FPGA design for use in TinyTapeout --- TinyTapeout/Makefile | 14 + TinyTapeout/constrainits.xdc | 721 ++++++++++++++++++++++++++ TinyTapeout/src/alu.vhd | 87 ++++ TinyTapeout/src/bfpu.v | 12 - TinyTapeout/src/bfpu.vhd | 202 ++++++++ TinyTapeout/src/branch.vhd | 122 +++++ TinyTapeout/src/cellMemory.vhd | 42 ++ TinyTapeout/src/cells.v | 116 ----- TinyTapeout/src/config.tcl | 62 --- TinyTapeout/src/instructionMemory.vhd | 38 ++ TinyTapeout/src/memoryPointer.vhd | 35 ++ TinyTapeout/src/programCounter.vhd | 40 ++ TinyTapeout/tb/tb_bfpu.vhd | 59 +++ 13 files changed, 1360 insertions(+), 190 deletions(-) create mode 100644 TinyTapeout/Makefile create mode 100755 TinyTapeout/constrainits.xdc create mode 100644 TinyTapeout/src/alu.vhd delete mode 100644 TinyTapeout/src/bfpu.v create mode 100644 TinyTapeout/src/bfpu.vhd create mode 100644 TinyTapeout/src/branch.vhd create mode 100644 TinyTapeout/src/cellMemory.vhd delete mode 100644 TinyTapeout/src/cells.v delete mode 100644 TinyTapeout/src/config.tcl create mode 100644 TinyTapeout/src/instructionMemory.vhd create mode 100644 TinyTapeout/src/memoryPointer.vhd create mode 100644 TinyTapeout/src/programCounter.vhd create mode 100644 TinyTapeout/tb/tb_bfpu.vhd diff --git a/TinyTapeout/Makefile b/TinyTapeout/Makefile new file mode 100644 index 0000000..fa960b5 --- /dev/null +++ b/TinyTapeout/Makefile @@ -0,0 +1,14 @@ +CHDL = ghdl +FLAGS = --std=08 +STOP = 90000ns + +all: tb/tb_bfpu.vhd src/bfpu.vhd + $(CHDL) -a $(FLAGS) src/alu.vhd src/branch.vhd src/cellMemory.vhd src/instructionMemory.vhd src/memoryPointer.vhd src/programCounter.vhd src/bfpu.vhd tb/tb_bfpu.vhd + $(CHDL) -e $(FLAGS) bfpu_tb + $(CHDL) -r $(FLAGS) bfpu_tb --wave=bpfu.ghw --stop-time=$(STOP) + +clean: + find . -name '*.o' -exec rm -r {} \; + find . -name '*.cf' -exec rm -r {} \; + find . -name '*.ghw' -exec rm -r {} \; + find . -name '*_tb' -exec rm -r {} \; diff --git a/TinyTapeout/constrainits.xdc b/TinyTapeout/constrainits.xdc new file mode 100755 index 0000000..9dec428 --- /dev/null +++ b/TinyTapeout/constrainits.xdc @@ -0,0 +1,721 @@ +## This file is a general .xdc for the Nexys4 rev B board +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal +##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch Wname = CLK100MHZ +set_property PACKAGE_PIN E3 [get_ports clk] + set_property IOSTANDARD LVCMOS33 [get_ports clk] + create_clock -add -name clk -period 10.00 -waveform {0 5} [get_ports clk] + +## Switches +##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 + set_property PACKAGE_PIN U9 [get_ports {sw[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] +##Bank = 34, Pin name = IO_25_34, Sch name = SW1 +set_property PACKAGE_PIN U8 [get_ports {sw[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] +##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 +set_property PACKAGE_PIN R7 [get_ports {sw[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] +##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 +set_property PACKAGE_PIN R6 [get_ports {sw[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] +##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 +set_property PACKAGE_PIN R5 [get_ports {sw[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] +##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 +set_property PACKAGE_PIN V7 [get_ports {sw[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] +##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 +set_property PACKAGE_PIN V6 [get_ports {sw[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] +##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 +set_property PACKAGE_PIN V5 [get_ports {sw[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] +##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 +#set_property PACKAGE_PIN U4 [get_ports {sw[8]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] +##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 +#set_property PACKAGE_PIN V2 [get_ports {sw[9]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] +##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 +#set_property PACKAGE_PIN U2 [get_ports {sw[10]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] +##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 +#set_property PACKAGE_PIN T3 [get_ports {sw[11]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] +##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 +#set_property PACKAGE_PIN T1 [get_ports {sw[12]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] +##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 +#set_property PACKAGE_PIN R3 [get_ports {sw[13]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] +##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 +#set_property PACKAGE_PIN P3 [get_ports {sw[14]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] +##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 +#set_property PACKAGE_PIN P4 [get_ports {sw[15]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + + +## LEDs +##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 +set_property PACKAGE_PIN T8 [get_ports {led[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] +#Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 +set_property PACKAGE_PIN V9 [get_ports {led[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] +#Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 + set_property PACKAGE_PIN R8 [get_ports {led[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] +#Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 + set_property PACKAGE_PIN T6 [get_ports {led[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] +#Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 +set_property PACKAGE_PIN T5 [get_ports {led[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] +#Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 +set_property PACKAGE_PIN T4 [get_ports {led[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] +#Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 +set_property PACKAGE_PIN U7 [get_ports {led[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] +#Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 +set_property PACKAGE_PIN U6 [get_ports {led[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] +#Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 +set_property PACKAGE_PIN V4 [get_ports {debug[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[0]}] +#Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 +set_property PACKAGE_PIN U3 [get_ports {debug[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[1]}] +#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 +set_property PACKAGE_PIN V1 [get_ports {debug[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[2]}] +#Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 +set_property PACKAGE_PIN R1 [get_ports {debug[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[3]}] +#Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 +set_property PACKAGE_PIN P5 [get_ports {debug[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[4]}] +#Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 +set_property PACKAGE_PIN U1 [get_ports {debug[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[5]}] +#Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 +set_property PACKAGE_PIN R2 [get_ports {debug[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[6]}] +#Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 +set_property PACKAGE_PIN P2 [get_ports {debug[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[7]}] + +##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R +#set_property PACKAGE_PIN K5 [get_ports {rgb[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[0]}] +##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G +#set_property PACKAGE_PIN F13 [get_ports {rgb[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[1]}] +##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B +#set_property PACKAGE_PIN F6 [get_ports {rgb[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[2]}] +##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R +#set_property PACKAGE_PIN K6 [get_ports {rgb[3]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[3]}] +##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G +#set_property PACKAGE_PIN H6 [get_ports {rgb[4]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[4]}] +##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B +#set_property PACKAGE_PIN L16 [get_ports {rgb[5]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {rgb[5]}] + + + +##7 segment display +##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA +#set_property PACKAGE_PIN L3 [get_ports {seg[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] +##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB +#set_property PACKAGE_PIN N1 [get_ports {seg[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] +##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC +#set_property PACKAGE_PIN L5 [get_ports {seg[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] +##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD +#set_property PACKAGE_PIN L4 [get_ports {seg[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] +##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE +#set_property PACKAGE_PIN K3 [get_ports {seg[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] +##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF +#set_property PACKAGE_PIN M2 [get_ports {seg[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] +##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG +#set_property PACKAGE_PIN L6 [get_ports {seg[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + +##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP +#set_property PACKAGE_PIN M4 [get_ports dp] + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + +##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 +#set_property PACKAGE_PIN N6 [get_ports {an[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] +##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 +#set_property PACKAGE_PIN M6 [get_ports {an[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] +##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 +#set_property PACKAGE_PIN M3 [get_ports {an[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] +##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 +#set_property PACKAGE_PIN N5 [get_ports {an[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] +##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 +#set_property PACKAGE_PIN N2 [get_ports {an[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] +##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 +#set_property PACKAGE_PIN N4 [get_ports {an[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] +##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = ANyte_out6 +#set_property PACKAGE_PIN L1 [get_ports {an[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] +##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 +#set_property PACKAGE_PIN M1 [get_ports {an[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] + + + +##Buttons +##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET +#set_property PACKAGE_PIN C12 [get_ports reset] +# set_property IOSTANDARD LVCMOS33 [get_ports reset] +##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC +#set_property PACKAGE_PIN E16 [get_ports clk] +# set_property IOSTANDARD LVCMOS33 [get_ports clk] +##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU +#set_property PACKAGE_PIN F15 [get_ports btnU] + #set_property IOSTANDARD LVCMOS33 [get_ports btnU] +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL +#set_property PACKAGE_PIN T16 [get_ports btnL] + #set_property IOSTANDARD LVCMOS33 [get_ports btnL] +##Bank = 14, Pin name = IO_25_14, Sch name = BTNR +#set_property PACKAGE_PIN R10 [get_ports btnR] + #set_property IOSTANDARD LVCMOS33 [get_ports btnR] +##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND +#set_property PACKAGE_PIN V10 [get_ports btnD] + #set_property IOSTANDARD LVCMOS33 [get_ports btnD] + + + +##Pmod Header JA +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 +#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] +##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 +#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] +##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 +#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] +##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 +#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] +##Bank = 15, Pin name = IO_0_15, Sch name = JA7 +#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] +##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 +#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] +##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 +#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] +##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 +#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + +##Pmod Header JB +##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 +#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] +##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 +#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] +##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 +#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] +##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 +#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] +##Bank = 15, Pin name = IO_25_15, Sch name = JB7 +#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] +##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 +#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] +##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 +#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] +##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 +#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + +##Pmod Header JC +##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 +#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] +##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 +#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] +##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 +#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] +##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 +#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] +##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 +#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] +##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 +#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] +##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 +#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] +##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 +#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + + +##Pmod Header JD +##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 +#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] +##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 +#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] +##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 +#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] +##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 +#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] +##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 +#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] +##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 +#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] +##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 +#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] +##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 +#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] + + + +##Pmod Header JXADC +##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P +#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] +##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P +#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] +##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P +#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] +##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P +#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] +##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N +#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] +##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N +#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] +##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N +#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] +##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N +#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + +##VGA Connector +##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 +#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] +##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 +#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] +##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 +#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] +##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 +#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] +##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 +#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] +##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 +#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] +##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 +#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] +##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 +#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] +##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 +#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] +##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 +#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] +# set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] +##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 +#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] +##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 +#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] +##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS +#set_property PACKAGE_PIN B11 [get_ports Hsync] +# set_property IOSTANDARD LVCMOS33 [get_ports Hsync] +##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS +#set_property PACKAGE_PIN B12 [get_ports Vsync] +# set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + + +##Micro SD Connector +##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET +#set_property PACKAGE_PIN E2 [get_ports sdReset] + #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] +##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD +#set_property PACKAGE_PIN A1 [get_ports sdCD] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] +##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK +#set_property PACKAGE_PIN B1 [get_ports sdSCK] + #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] +##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD +#set_property PACKAGE_PIN C1 [get_ports sdCmd] + #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] +##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 +#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] +##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 +#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] +##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 +#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] +##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 +#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] + + + +##Accelerometer +##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO +#set_property PACKAGE_PIN D13 [get_ports MISO] +# set_property IOSTANDARD LVCMOS33 [get_ports MISO] +#Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI +#set_property PACKAGE_PIN B14 [get_ports MOSI] +# set_property IOSTANDARD LVCMOS33 [get_ports MOSI] +#Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK +#set_property PACKAGE_PIN D15 [get_ports SCLK] +# set_property IOSTANDARD LVCMOS33 [get_ports SCLK] +#Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN +#set_property PACKAGE_PIN C15 [get_ports SS] +# set_property IOSTANDARD LVCMOS33 [get_ports SS] +##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 +#set_property PACKAGE_PIN C16 [get_ports aclInt1] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] +##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 +#set_property PACKAGE_PIN E15 [get_ports aclInt2] + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] + + + +##Temperature Sensor +##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL +#set_property PACKAGE_PIN F16 [get_ports tmpSCL] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] +##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA +#set_property PACKAGE_PIN G16 [get_ports tmpSDA] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] +##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT +#set_property PACKAGE_PIN D14 [get_ports tmpInt] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT +#set_property PACKAGE_PIN C14 [get_ports tmpCT] + #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] + + + +##Omnidirectional Microphone +##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK +#set_property PACKAGE_PIN J5 [get_ports micClk] + #set_property IOSTANDARD LVCMOS33 [get_ports micClk] +##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA +#set_property PACKAGE_PIN H5 [get_ports micData] + #set_property IOSTANDARD LVCMOS33 [get_ports micData] +##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL +#set_property PACKAGE_PIN F5 [get_ports micLRSel] + #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] + + + +##PWM Audio Amplifier +##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM +#set_property PACKAGE_PIN A11 [get_ports ampPWM] + #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] +##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD +#set_property PACKAGE_PIN D12 [get_ports ampSD] + #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] + + +##USB-RS232 Interface +##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN +#set_property PACKAGE_PIN C4 [get_ports RsRx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] +##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT +#set_property PACKAGE_PIN D4 [get_ports RsTx] + #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] +##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS +#set_property PACKAGE_PIN D3 [get_ports RsCts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] +##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS +#set_property PACKAGE_PIN E5 [get_ports RsRts] + #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] + + + +##USB HID (PS/2) +##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK +#set_property PACKAGE_PIN F4 [get_ports PS2Clk] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + #set_property PULLUP true [get_ports PS2Clk] +##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA +#set_property PACKAGE_PIN B2 [get_ports PS2Data] + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + #set_property PULLUP true [get_ports PS2Data] + + + +##SMSC Ethernet PHY +##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC +#set_property PACKAGE_PIN C9 [get_ports PhyMdc] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] +##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO +#set_property PACKAGE_PIN A9 [get_ports PhyMdio] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] +##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN +#set_property PACKAGE_PIN B3 [get_ports PhyRstn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] +##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV +#set_property PACKAGE_PIN D9 [get_ports PhyCrs] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] +##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR +#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] +##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 +#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] +##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 +#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] +##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN +#set_property PACKAGE_PIN B9 [get_ports PhyTxEn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] +##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 +#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] +##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 +#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] +##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK +#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] +##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN +#set_property PACKAGE_PIN B8 [get_ports PhyIntn] + #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] + + + +##Quad SPI Flash +##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK +#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] +##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 +#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] +##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 +#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] +##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 +#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] +##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 +#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN +#set_property PACKAGE_PIN L13 [get_ports QspiCSn] + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + + +##Cellular RAM +##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK +#set_property PACKAGE_PIN T15 [get_ports RamCLK] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK] +##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN +#set_property PACKAGE_PIN T13 [get_ports RamADVn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn] +##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN +#set_property PACKAGE_PIN L18 [get_ports RamCEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn] +##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE +#set_property PACKAGE_PIN J14 [get_ports RamCRE] + #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] +##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN +#set_property PACKAGE_PIN H14 [get_ports RamOEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn] +##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN +#set_property PACKAGE_PIN R11 [get_ports RamWEn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn] +##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN +#set_property PACKAGE_PIN J15 [get_ports RamLBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn] +##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN +#set_property PACKAGE_PIN J13 [get_ports RamUBn] + #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn] +##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT +#set_property PACKAGE_PIN T14 [get_ports RamWait] + #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] + +##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 +#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}] +##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 +#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}] +##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 +#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}] +##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 +#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}] +##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 +#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}] +##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 +#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}] +##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 +#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}] +##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 +#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}] +##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 +#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}] +##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 +#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}] +##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 +#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}] +##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 +#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}] +##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 +#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}] +##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 +#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}] +##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 +#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}] +##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 +#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}] + +##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 +#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}] +##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 +#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}] +##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 +#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}] +##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 +#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}] +##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 +#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}] +##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 +#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}] +##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 +#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}] +##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 +#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}] +##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 +#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}] +##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 +#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}] +##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 +#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}] +##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 +#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}] +##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 +#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}] +##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 +#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}] +##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 +#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}] +##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 +#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}] +##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 +#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}] +##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 +#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}] +##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 +#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}] +##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 +#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}] +##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 +#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}] +##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 +#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] +##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 +#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] + #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}] diff --git a/TinyTapeout/src/alu.vhd b/TinyTapeout/src/alu.vhd new file mode 100644 index 0000000..d6d36ad --- /dev/null +++ b/TinyTapeout/src/alu.vhd @@ -0,0 +1,87 @@ +-- alu.vhd +-- Created on: Di 26. Sep 10:07:59 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Decode instructions and control brainfuck logic +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity alu: alu crtl +entity alu is + port( + instruction : in std_logic_vector(2 downto 0); + old_cell : in std_logic_vector(7 downto 0); + old_pointer : in std_logic_vector(15 downto 0); + extern_in : in std_logic_vector(7 downto 0); + + new_cell : out std_logic_vector(7 downto 0); + new_pointer : out std_logic_vector(15 downto 0); + enable_cell : out std_logic; + enable_ptr : out std_logic; + extern_out : out std_logic_vector(7 downto 0) + ); +end alu; + +-- Architecture implementation of alu: implements table +architecture implementation of alu is + signal buffer_out : std_logic_vector(7 downto 0) := (others => '0'); +begin + -- Process p_instruction + p_instruction : process (extern_in, instruction, old_cell, old_pointer) + begin + case instruction is + when "000" => + enable_cell <= '0'; + enable_ptr <= '1'; + new_pointer <= std_logic_vector(unsigned(old_pointer) + 1); + + new_cell <= old_cell; + -- buffer_out <= "00000000"; + when "001" => + enable_cell <= '0'; + enable_ptr <= '1'; + new_pointer <= std_logic_vector(unsigned(old_pointer) - 1); + + new_cell <= old_cell; + -- buffer_out <= "00000000"; + when "010" => + enable_cell <= '1'; + enable_ptr <= '0'; + new_cell <= std_logic_vector(unsigned(old_cell) + 1); + + new_pointer <= old_pointer; + -- buffer_out <= "00000000"; + when "011" => + enable_cell <= '1'; + enable_ptr <= '0'; + new_cell <= std_logic_vector(unsigned(old_cell) - 1); + + new_pointer <= old_pointer; + -- buffer_out <= "00000000"; + when "100" => + enable_cell <= '1'; + enable_ptr <= '0'; + new_cell <= extern_in; + + new_pointer <= old_pointer; + -- buffer_out <= "00000000"; + when "101" => + enable_cell <= '0'; + enable_ptr <= '0'; + buffer_out <= old_cell; + + new_pointer <= old_pointer; + new_cell <= old_cell; + when others => + enable_cell <= '0'; + enable_ptr <= '0'; + + new_pointer <= old_pointer; + new_cell <= old_cell; + -- buffer_out <= "00000000"; + end case; + end process; + + extern_out <= buffer_out; + +end implementation; diff --git a/TinyTapeout/src/bfpu.v b/TinyTapeout/src/bfpu.v deleted file mode 100644 index 4c529fb..0000000 --- a/TinyTapeout/src/bfpu.v +++ /dev/null @@ -1,12 +0,0 @@ -module tt_um_yannickreiss_bfpu(input wire [7:0] ui_in, // Dedicated inputs - output wire [7:0] uo_out, // Dedicated outputs - input wire [7:0] uio_in, // IOs: Input path - output wire [7:0] uio_out, // IOs: Output path - output wire [7:0] uio_oe, // IOs: Enable path (active high: 0 = input, 1 = output - input wire ena, - input wire clk, - input wire rst_n); - - - -endmodule diff --git a/TinyTapeout/src/bfpu.vhd b/TinyTapeout/src/bfpu.vhd new file mode 100644 index 0000000..6af19b6 --- /dev/null +++ b/TinyTapeout/src/bfpu.vhd @@ -0,0 +1,202 @@ +-- bfpu.vhd +-- Created on: Di 26. Sep 08:27:47 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Connect the entities of the processing unit. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity bfpu: brainfuck processing unit +entity bfpu is + port( + clk : in std_logic; -- board clock + sw : in std_logic_vector(7 downto 0); -- Input for instruction , + debug : out std_logic_vector(7 downto 0); -- Value of currently selected logic cell. + led : out std_logic_vector(7 downto 0) -- Output for instruction . + ); +end bfpu; + +-- Architecture arch of bfpu: setup and connect components +architecture arch of bfpu is + + component instructionMemory + port( + instructionAddr : in std_logic_vector(7 downto 0); + instruction : out std_logic_vector(2 downto 0) + ); + end component; + + component alu + port( + instruction : in std_logic_vector(2 downto 0); + old_cell : in std_logic_vector(7 downto 0); + old_pointer : in std_logic_vector(15 downto 0); + extern_in : in std_logic_vector(7 downto 0); + + new_cell : out std_logic_vector(7 downto 0); + new_pointer : out std_logic_vector(15 downto 0); + enable_cell : out std_logic; + enable_ptr : out std_logic; + extern_out : out std_logic_vector(7 downto 0) + ); + end component; + + component ptr + port( + clk : in std_logic; + enable_ptr : in std_logic; + new_ptr : in std_logic_vector(15 downto 0); + old_ptr : out std_logic_vector(15 downto 0) + ); + end component; + + component cellblock + port( + clk : in std_logic; + enable : in std_logic; + address : in std_logic_vector(15 downto 0); + new_cell : in std_logic_vector(7 downto 0); + old_cell : out std_logic_vector(7 downto 0) + ); + end component; + + component program_counter + port( + clk : in std_logic; + enable : in std_logic; + jmp : in std_logic; + pc_in : in std_logic_vector(7 downto 0); + pc_out : out std_logic_vector(7 downto 0) + ); + end component; + + component branch + port( + clk : in std_logic; + state : in std_logic; + instruction : in std_logic_vector(2 downto 0); + instr_addr : in std_logic_vector(7 downto 0); + cell_value : in std_logic_vector(7 downto 0); + + skip : out std_logic; + jump : out std_logic; + pc_enable : out std_logic; + pc_out : out std_logic_vector(7 downto 0) + ); + end component; + + signal s_clk : std_logic; + signal s_in : std_logic_vector(7 downto 0) := (others => '0'); + signal s_out : std_logic_vector(7 downto 0) := (others => '0'); + + signal s_instrAddr : std_logic_vector(7 downto 0) := "00000000"; + signal s_instruction : std_logic_vector(2 downto 0) := "000"; + + signal s_cell_out : std_logic_vector(7 downto 0) := (others => '0'); + signal s_cell_in : std_logic_vector(7 downto 0) := (others => '0'); + signal s_ptr_out : std_logic_vector(15 downto 0) := (others => '0'); + signal s_ptr_in : std_logic_vector(15 downto 0) := (others => '0'); + + signal s_enable_cells : std_logic := '0'; + signal s_enable_ptr : std_logic := '0'; + + signal s_enable_pc : std_logic := '1'; + signal s_jmp_pc : std_logic := '0'; + signal s_jmp_addr_pc : std_logic_vector(7 downto 0) := "00000000"; + + signal s_skip : std_logic := '0'; + signal s_enable_cells_o : std_logic := '0'; + signal s_enable_ptr_o : std_logic := '0'; + + signal processor_state : std_logic := '0'; -- 0: execute; 1: write back + +begin + + -- clock and state logic + s_clk <= clk; + -- Process state change state between execute and write back + state : process (s_clk) -- runs only, when s_clk changed + begin + if rising_edge(s_clk) then + processor_state <= not processor_state; + end if; + end process; + + -- Process in_out set in- and output on clk high and exec/write back + in_out : process (s_clk) -- runs only, when s_clk changed + begin + if rising_edge(s_clk) then + if processor_state = '1' then + led <= s_out; + else + s_in <= sw; + end if; + end if; + end process; + + + + instrMemory : instructionMemory + port map( + instructionAddr => s_instrAddr, + instruction => s_instruction + ); + + alu_entity : alu + port map( + instruction => s_instruction, + old_cell => s_cell_out, + old_pointer => s_ptr_out, + extern_in => s_in, + + new_cell => s_cell_in, + new_pointer => s_ptr_in, + enable_cell => s_enable_cells_o, + enable_ptr => s_enable_ptr_o, + extern_out => s_out + ); + + ptr_bf : ptr + port map( + clk => s_clk, + enable_ptr => s_enable_ptr, + new_ptr => s_ptr_in, + old_ptr => s_ptr_out + ); + + cellblock_bf : cellblock + port map( + clk => s_clk, + enable => s_enable_cells, + address => s_ptr_out, + new_cell => s_cell_in, + old_cell => s_cell_out + ); + + pc : program_counter + port map( + clk => s_clk, + enable => s_enable_pc and processor_state, + jmp => s_jmp_pc, + pc_in => s_jmp_addr_pc, + pc_out => s_instrAddr + ); + + branch_bf : branch + port map( + clk => s_clk, + state => processor_state, + instruction => s_instruction, + instr_addr => s_instrAddr, + cell_value => s_cell_out, + skip => s_skip, + jump => s_jmp_pc, + pc_enable => s_enable_pc, + pc_out => s_jmp_addr_pc + ); + + s_enable_ptr <= not s_skip and s_enable_ptr_o and processor_state; + s_enable_cells <= not s_skip and s_enable_cells_o and processor_state; + debug <= s_cell_out; + +end arch; diff --git a/TinyTapeout/src/branch.vhd b/TinyTapeout/src/branch.vhd new file mode 100644 index 0000000..f78b8c7 --- /dev/null +++ b/TinyTapeout/src/branch.vhd @@ -0,0 +1,122 @@ +-- branch.vhd +-- Created on: Di 26. Sep 13:47:51 CEST 2023 +-- Author(s): Yannick Reiss +-- Content: Branch unit / ALU for program counter XD +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- TODO: CHECK PUSH AND POP AND THE PHASES/STATES OF PC_ENABLE + +-- Entity branch: branch +entity branch is + port( + clk : in std_logic; + state : in std_logic; + instruction : in std_logic_vector(2 downto 0); + instr_addr : in std_logic_vector(7 downto 0); + cell_value : in std_logic_vector(7 downto 0); + + skip : out std_logic; + pc_enable : out std_logic; + jump : out std_logic; + pc_out : out std_logic_vector(7 downto 0) + ); +end branch; + +-- Architecture impl of branch: +architecture impl of branch is + type stack is array(0 to 255) of std_logic_vector(7 downto 0); + + signal addr_stack : stack := (others => (others => '0')); + signal nested : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops + signal skip_internal : std_logic := '0'; + signal stack_ptr : std_logic_vector(7 downto 0) := (others => '0'); + signal pc_enable_internal : std_logic := '1'; + +begin + + -- Process branch_compute Thing that does things. + branch_compute : process (all) -- runs only, when all changed + begin + if rising_edge(clk) then + + -- set addr_stack + if skip = '0' then + -- pop part 1 + + -- push part 2 + if state = '1' and instruction = "110" then + addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr; + end if; + end if; + + -- set nested + if state = '0' and skip_internal = '1' then + + -- deeper nest + if instruction = "110" then + nested <= std_logic_vector(unsigned(nested) + 1); + end if; + end if; + + if state = '1' and skip_internal = '1' then + -- nested loop ended + if instruction = "111" then + nested <= std_logic_vector(unsigned(nested) - 1); + end if; + end if; + + -- set skip + -- on instruction [ + if instruction = "110" and state = '0' then + if unsigned(cell_value) > 0 and not ( skip_internal = '1' or unsigned(nested) > 0 ) then + skip_internal <= '0'; + else + skip_internal <= '1'; + end if; + end if; + + -- on instruction ] + if state = '0' and instruction = "111" then + if skip_internal = '1' and unsigned(nested) > 0 then + skip_internal <= '1'; + else + skip_internal <= '0'; + end if; + end if; + + -- set stack_ptr + if skip_internal = '0' then + -- pop part 2 + if state = '1' and instruction = "111" then + stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1); + end if; + + -- push part 1 + if state = '0' and instruction = "110" then + stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1); + end if; + end if; + + + -- set pc_enable + pc_enable_internal <= not state; + + -- set jump + if instruction = "111" and skip = '0' and state = '0' then + jump <= '1'; + else + jump <= '0'; + end if; + + + end if; + end process; + + -- connect signals to pins + skip <= skip_internal; + pc_enable <= pc_enable_internal; + pc_out <= addr_stack(to_integer(unsigned(stack_ptr))); + +end impl; diff --git a/TinyTapeout/src/cellMemory.vhd b/TinyTapeout/src/cellMemory.vhd new file mode 100644 index 0000000..d6b7e40 --- /dev/null +++ b/TinyTapeout/src/cellMemory.vhd @@ -0,0 +1,42 @@ +-- cellMemory.vhd +-- Created on: Di 26. Sep 11:39:10 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Cell memory as part of brainfuck logic +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +-- Entity cellblock +entity cellblock is + + port( + clk : in std_logic; -- clock with speed of board clock + enable : in std_logic; + address : in std_logic_vector(15 downto 0); + new_cell : in std_logic_vector(7 downto 0); + + old_cell : out std_logic_vector(7 downto 0) + ); +end cellblock; + +-- Architecture arch of cellblock: read on every clock cycle to cell. +architecture arch of cellblock is + type empty is array(0 to 65535) of std_logic_vector(7 downto 0); + + signal memory : empty := (others => (others => '0')); + +begin + -- Process clk_read + clk_read : process (clk, enable) -- runs only, when clk changed + begin + + if rising_edge(clk) and enable = '1' then + memory(to_integer(unsigned(address))) <= new_cell; + end if; + + end process; + + old_cell <= memory(to_integer(unsigned(address))); + +end arch; diff --git a/TinyTapeout/src/cells.v b/TinyTapeout/src/cells.v deleted file mode 100644 index a009418..0000000 --- a/TinyTapeout/src/cells.v +++ /dev/null @@ -1,116 +0,0 @@ -/* - This file provides the mapping from the Wokwi modules to Verilog HDL - - It's only needed for Wokwi designs - - */ -`define default_netname none - -// custom cells -module reg_cell (input wire clk, - input wire d, - output wire q); - reg register; - - always @(posedge clk) begin - register = d; - end - - assign q = register; -endmodule // reg_cell - - // TinyTapeout cells - module buffer_cell ( - input wire in, - output wire out - ); - assign out = in; - endmodule - - module and_cell ( - input wire a, - input wire b, - output wire out - ); - - assign out = a & b; - endmodule - - module or_cell ( - input wire a, - input wire b, - output wire out - ); - - assign out = a | b; - endmodule - - module xor_cell ( - input wire a, - input wire b, - output wire out - ); - - assign out = a ^ b; - endmodule - - module nand_cell ( - input wire a, - input wire b, - output wire out - ); - - assign out = !(a&b); - endmodule - - module not_cell ( - input wire in, - output wire out - ); - - assign out = !in; - endmodule - - module mux_cell ( - input wire a, - input wire b, - input wire sel, - output wire out - ); - - assign out = sel ? b : a; - endmodule - - module dff_cell ( - input wire clk, - input wire d, - output reg q, - output wire notq - ); - - assign notq = !q; - always @(posedge clk) - q <= d; - - endmodule - - module dffsr_cell ( - input wire clk, - input wire d, - input wire s, - input wire r, - output reg q, - output wire notq - ); - - assign notq = !q; - - always @(posedge clk or posedge s or posedge r) begin - if (r) - q <= 0; - else if (s) - q <= 1; - else - q <= d; - end - endmodule diff --git a/TinyTapeout/src/config.tcl b/TinyTapeout/src/config.tcl deleted file mode 100644 index a1a1515..0000000 --- a/TinyTapeout/src/config.tcl +++ /dev/null @@ -1,62 +0,0 @@ -# PLEASE DO NOT EDIT THIS FILE! -# If you get stuck with this config, please open an issue or get in touch via the discord. - -# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html - -# User config -set script_dir [file dirname [file normalize [info script]]] - -# read some user config that is written by the setup.py program. -# - the name of the module is defined -# - the list of source files -source $::env(DESIGN_DIR)/user_config.tcl - -# save some time -set ::env(RUN_KLAYOUT_XOR) 0 -set ::env(RUN_KLAYOUT_DRC) 0 - -# don't put clock buffers on the outputs -set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0 - -# allow use of specific sky130 cells -set ::env(SYNTH_READ_BLACKBOX_LIB) 1 - -# reduce wasted space -set ::env(TOP_MARGIN_MULT) 1 -set ::env(BOTTOM_MARGIN_MULT) 1 -set ::env(LEFT_MARGIN_MULT) 6 -set ::env(RIGHT_MARGIN_MULT) 6 - -# absolute die size -set ::env(FP_SIZING) absolute - -set ::env(PL_BASIC_PLACEMENT) {0} -set ::env(GRT_ALLOW_CONGESTION) "1" - -# otherwise fails on small designs at global placement -set ::env(GRT_CELL_PADDING) "4" - -set ::env(FP_IO_HLENGTH) 2 -set ::env(FP_IO_VLENGTH) 2 - -# use alternative efabless decap cells to solve LI density issue -set ::env(DECAP_CELL) "\ - sky130_fd_sc_hd__decap_3 \ - sky130_fd_sc_hd__decap_4 \ - sky130_fd_sc_hd__decap_6 \ - sky130_fd_sc_hd__decap_8 \ - sky130_ef_sc_hd__decap_12" - -# clock -set ::env(CLOCK_TREE_SYNTH) 1 -# period is in ns, so 20ns == 50mHz -set ::env(CLOCK_PERIOD) "20" -set ::env(CLOCK_PORT) {clk} - -# hold/slack margin -# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8 -# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8 - -# don't use power rings or met5 -set ::env(DESIGN_IS_CORE) 0 -set ::env(RT_MAX_LAYER) {met4} diff --git a/TinyTapeout/src/instructionMemory.vhd b/TinyTapeout/src/instructionMemory.vhd new file mode 100644 index 0000000..2facc73 --- /dev/null +++ b/TinyTapeout/src/instructionMemory.vhd @@ -0,0 +1,38 @@ +-- instructionMemory.vhd +-- Created on: Di 26. Sep 07:43:20 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Instruction memory; Read and write operations are controlled externally. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity instructionMemory: Currently ROM; TODO: Add write enable when implementing a bus. +entity instructionMemory is + + port( + instructionAddr : in std_logic_vector(7 downto 0); -- We start with 256 instructions + + instruction : out std_logic_vector(2 downto 0) -- instruction in current cell + ); +end instructionMemory; + +-- Architecture arch of instructionMemory: read on every clock cycle to instruction. +architecture arch of instructionMemory is + + type imem is array(0 to 255) of std_logic_vector(2 downto 0); + signal memory : imem := (b"010",b"001",b"010",b"000",b"011",b"001",b"011",b"000",b"110",b"011",b"111",b"011",b"110",b"011",b"101",b"111",others=>"000"); +begin + -- Process clk_read +-- clk_read : process (clk) -- runs only, when clk changed +-- begin +-- +-- if rising_edge(clk) then +-- +-- instruction <= memory(to_integer(unsigned(instructionAddr))); +-- +-- end if; +-- end process; + + instruction <= memory(to_integer(unsigned(instructionAddr))); + +end arch; diff --git a/TinyTapeout/src/memoryPointer.vhd b/TinyTapeout/src/memoryPointer.vhd new file mode 100644 index 0000000..e63b258 --- /dev/null +++ b/TinyTapeout/src/memoryPointer.vhd @@ -0,0 +1,35 @@ +-- memoryPointer.vhd +-- Created on: Di 26. Sep 11:11:49 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Store current ptr. Part of brainfuck logic +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity ptr: 15 bit pointer to cell +entity ptr is + port( + clk : in std_logic; + enable_ptr : in std_logic; + new_ptr : in std_logic_vector(15 downto 0); + + old_ptr : out std_logic_vector(15 downto 0) + ); +end ptr; + +-- Architecture implement_ptr of ptr: +architecture implement_ptr of ptr is + signal reg : std_logic_vector(15 downto 0) := (others => '0'); +begin + + -- Process Write set new_ptr + write : process (clk, enable_ptr) -- runs only, when clk changed + begin + if rising_edge(clk) and enable_ptr = '1' then + reg <= new_ptr; + end if; + end process; + + old_ptr <= reg; + +end implement_ptr; diff --git a/TinyTapeout/src/programCounter.vhd b/TinyTapeout/src/programCounter.vhd new file mode 100644 index 0000000..5846e07 --- /dev/null +++ b/TinyTapeout/src/programCounter.vhd @@ -0,0 +1,40 @@ +-- programCounter.vhd +-- Created on: Di 26. Sep 12:45:10 CEST 2023 +-- Author(s): Yannick Reiß +-- Content: Set and store program counter only. Logic entirely in branch! +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +-- Entity program_counter: set/store pc +entity program_counter is + port( + clk : in std_logic; + enable : in std_logic; + jmp : in std_logic; + pc_in : in std_logic_vector(7 downto 0); + pc_out : out std_logic_vector(7 downto 0) + ); +end program_counter; + +-- Architecture pc of program_counter: +architecture pc of program_counter is + signal pc_intern : std_logic_vector(7 downto 0) := (others => '0'); +begin + + -- Process count + count : process (clk, enable, jmp) -- runs only, when clk, enable, jmp changed + begin + if rising_edge(clk) and enable = '1' then + if jmp = '1' then + pc_intern <= pc_in; + else + pc_intern <= std_logic_vector(unsigned(pc_intern) + 1); + end if; + end if; + end process; + + + pc_out <= pc_intern; + +end pc; diff --git a/TinyTapeout/tb/tb_bfpu.vhd b/TinyTapeout/tb/tb_bfpu.vhd new file mode 100644 index 0000000..ad9dcdb --- /dev/null +++ b/TinyTapeout/tb/tb_bfpu.vhd @@ -0,0 +1,59 @@ +-- tb_bfpu +-- 2023-10-04 +-- Author: Yannick Reiß +-- E-Mail: yannick.reiss@protonmail.ch +-- Copyright: MIT +-- Content: Entity tb_bfpu - Run bfpu for testbench. +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library std; +use std.textio.all; + +entity bfpu_tb is +end bfpu_tb; + +architecture implementation of bfpu_tb is + + -- input + signal clk : std_logic; + signal sw : std_logic_vector(7 downto 0); + + -- output + signal debug : std_logic_vector(7 downto 0); + signal led : std_logic_vector(7 downto 0); + + constant clk_period : time := 10 ns; + +begin + + uut : entity work.bfpu(arch) + port map ( + clk => clk, + sw => sw, + debug => debug, + led => led); + + sw <= "00001011"; + + -- Clock process definitions + clk_process : process + begin + clk <= '0'; + wait for clk_period / 2; + clk <= '1'; + wait for clk_period / 2; + end process; + + -- Process stim_proc + stim_proc : process + variable lineBuffer : line; + begin + write(lineBuffer, string'("Start the simulator")); + writeline(output, lineBuffer); + + wait; + end process; + +end implementation ; -- implementation