diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd
index d44b3ff..f78b8c7 100644
--- a/fpga/src/branch.vhd
+++ b/fpga/src/branch.vhd
@@ -58,7 +58,9 @@ begin
                 if instruction = "110" then
                     nested <= std_logic_vector(unsigned(nested) + 1);
                 end if;
+            end if;
 
+            if state = '1' and skip_internal = '1' then
                 -- nested loop ended
                 if instruction = "111" then
                     nested <= std_logic_vector(unsigned(nested) - 1);
diff --git a/fpga/src/instructionMemory.vhd b/fpga/src/instructionMemory.vhd
index 08dd7cc..2facc73 100644
--- a/fpga/src/instructionMemory.vhd
+++ b/fpga/src/instructionMemory.vhd
@@ -20,7 +20,7 @@ end instructionMemory;
 architecture arch of instructionMemory is
 
     type imem is array(0 to 255) of std_logic_vector(2 downto 0);
-    signal memory : imem := (b"010",b"110",b"000",b"011",b"110",b"101",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"000",b"011",b"110",b"011",b"111",b"001",b"111",b"001",b"111",b"001",b"111",b"001",b"111",others=>"000");
+    signal memory : imem := (b"010",b"001",b"010",b"000",b"011",b"001",b"011",b"000",b"110",b"011",b"111",b"011",b"110",b"011",b"101",b"111",others=>"000");
 begin
     -- Process clk_read
 --    clk_read : process (clk) -- runs only, when clk changed