Add systemverilog basic module creation

UltiSnips/systemverilog.snippets

@@ -0,0 +1,32 @@
+extends verilog
+
+priority 300
+
+snippet module "Define a new module" b
+module ${1:`!p snip.rv = fn.split(".")[0]`}`!p if t[2] == "":
+	snip.rv = ""
+else:
+	snip.rv = " #("`${2:parameter p0 = 5}`!p if t[2] == "":
+	snip.rv = ""
+else:
+	snip.rv = ") "``!p if t[3] == "":
+	snip.rv = ""
+else:
+	snip.rv = "("`${3:input wire clk}`!p if t[3] == "":
+	snip.rv = ""
+else:
+	snip.rv = ")"`;`!p
+if t[3] == "":
+	snip.rv = t[3]
+else:
+	no_break = t[3].replace("\n", "")
+	io_break = no_break.replace("input", "\n\tinput")
+	io_break = io_break.replace("output", "\n\toutput")
+	t[3] = io_break
+`
+	$0
+	// `!p snip.rv = t[1]`
+	// `!p snip.rv = t[2]`
+	// `!p snip.rv = t[3]`
+endmodule
+endsnippet