VHDL LSP integration update

2025-10-22 20:38:43 +02:00
parent 19b0ce44bc
commit 7b3f516848
6 changed files with 40 additions and 1 deletions
--- a/UltiSnips/lean.snippets
+++ b/UltiSnips/lean.snippets
@@ -35,3 +35,7 @@ endsnippet
 snippet A "All"
 ∀
 endsnippet
+
+snippet . "Dot"
+·
+endsnippet
--- a/UltiSnips/veryl.snippets
+++ b/UltiSnips/veryl.snippets
@@ -0,0 +1,13 @@
+snippet module "Create a new module" b
+${1:pub } module ${2:module_name} (
+	$3
+) {
+	$0
+	}
+endsnippet
+
+snippet embed "Add embed"
+embed (inline) sv{{{
+	$1
+}}}$0
+endsnippet