Update Verilog snippets

2023-08-26 08:21:47 +02:00
parent a4bd9d253b
commit 583d6f9790
5 changed files with 15 additions and 0 deletions
--- a/UltiSnips/verilog.snippets
+++ b/UltiSnips/verilog.snippets
@@ -42,3 +42,15 @@ endsnippet
 snippet ,double "set bus to size of a double word" A
 [63:0]$0
 endsnippet
+
+snippet begin "begin - end" iA
+begin
+	$1
+end
+$0
+endsnippet
+
+snippet def "Definition/Constant" b
+\`define ${1:NAME} ${2:VALUE}
+$0
+endsnippet