stackprocessor/tb_alu.vhdl

-- tb_alu.vhdl
-- Date:   Sun Mar  3 09:47:29 2024
-- Author:    Yannick Reiß
-- E-Mail:    yannick.reiss@nickr.eu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library std;
use std.textio.all;

library work;

entity alu_tb is
end alu_tb;

architecture Testbench of alu_tb is

  signal clk          : std_logic;
  constant clk_period : time                         := 10 ns;
  signal operator     : std_logic_vector(5 downto 0) := "111111";
  signal operand1     : std_logic_vector(7 downto 0) := (others => '0');
  signal operand2     : std_logic_vector(7 downto 0) := (others => '0');
  signal target       : std_logic_vector(7 downto 0) := (others => '0');
  signal test_result  : std_logic                    := '0';
  signal result       : std_logic_vector(7 downto 0) := (others => '0');
begin

  uut : entity work.alu(Logic)
    port map (
      operator => operator,
      operand1 => operand1,
      operand2 => operand2,
      result   => result
      );

  clk_process : process
  begin
    clk <= '0';
    wait for clk_period/2;
    clk <= '1';
    wait for clk_period/2;
  end process;

  testing : process
    variable lineBuffer : line;
  begin
    wait until rising_edge(clk);
    write(lineBuffer, string'("Starting the simulator"));
    writeline(output, lineBuffer);

    -- Testcases
    operand1 <= std_logic_vector(to_unsigned(3, 8));
    operand2 <= std_logic_vector(to_unsigned(20, 8));

    -- Not
    wait for 5 ns;
    operator    <= "000000";
    target      <= operand1 xor "11111111";
    wait for 5 ns;
    if not (target = result) then
      write(lineBuffer, string'("Error on Not"));
      writeline(output, lineBuffer);
    end if;

    -- Parity
    wait for 5 ns;
    operator <= "000100";
    target   <= "00000000";
    wait for 5 ns;
    if not (unsigned(result) = unsigned(target)) then
      write(lineBuffer, string'("Error on Parity"));
      writeline(output, lineBuffer);
    end if;

    -- Count
    wait for 5 ns;
    operator <= "001000";
    target   <= "00000010";
    wait for 5 ns;
    if not (unsigned(result) = 1) then
      write(lineBuffer, string'("Error on Count"));
      writeline(output, lineBuffer);
    end if;

    -- And
    wait for 5 ns;
    operator <= "001101";
    target   <= operand1 and operand2;
    wait for 5 ns;
    if not (result = target) then
      write(lineBuffer, string'("Error on And"));
      writeline(output, lineBuffer);
    end if;

    -- Or
    wait for 5 ns;
    operator <= "010001";
    wait for 5 ns;
    if not (result = (operand1 or operand2)) then
      write(lineBuffer, string'("Error on Or"));
      writeline(output, lineBuffer);
    end if;

    -- Xor
    wait for 5 ns;
    operator <= "010101";
    wait for 5 ns;
    if not (result = (operand1 xor operand2)) then
      write(lineBuffer, string'("Error on Xor"));
      writeline(output, lineBuffer);
    end if;

    -- Move
    wait for 5 ns;
    operator <= "011001";
    wait for 5 ns;
    if not (result = operand2) then
      write(lineBuffer, string'("Error on Move"));
      writeline(output, lineBuffer);
    end if;

    -- Shift left
    wait for 5 ns;
    operator <= "011101";
    wait for 5 ns;
    if not (result = std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2))))) then
      write(lineBuffer, string'("Error on Shift left"));
      writeline(output, lineBuffer);
    end if;

    -- Shift right
    wait for 5 ns;
    operator <= "100001";
    wait for 5 ns;
    if not (result = std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2))))) then
      write(lineBuffer, string'("Error on Shift right"));
      writeline(output, lineBuffer);
    end if;

    -- Add
    wait for 5 ns;
    operator <= "000010";
    wait for 5 ns;
    if not (result = std_logic_vector(unsigned(operand1) + unsigned(operand2))) then
      write(lineBuffer, string'("Error on Add"));
      writeline(output, lineBuffer);
    end if;

    -- Sub
    wait for 5 ns;
    operator <= "000110";
    wait for 5 ns;
    if not (result = std_logic_vector(signed(operand1) - signed(operand2))) then
      write(lineBuffer, string'("Error on Sub"));
      writeline(output, lineBuffer);
    end if;

    -- Seq
    wait for 5 ns;
    operator <= "000011";
    wait for 5 ns;
    if not (result = "00000000") then
      write(lineBuffer, string'("Error on Set if Equal"));
      writeline(output, lineBuffer);
    end if;

    -- Slt
    wait for 5 ns;
    operator <= "000111";
    wait for 5 ns;
    if not (result = "00000001") then
      write(lineBuffer, string'("Error on Set if Lower"));
      writeline(output, lineBuffer);
    end if;

    -- Sltu
    wait for 5 ns;
    operator <= "001011";
    wait for 5 ns;
    if not (result = "00000001") then
      write(lineBuffer, string'("Error on Set if lower unsigned"));
      writeline(output, lineBuffer);
    end if;

    write(lineBuffer, string'("End of simulator"));
    writeline(output, lineBuffer);

    wait;
  end process;

end Testbench;