76 lines
1.7 KiB
VHDL
76 lines
1.7 KiB
VHDL
-- tb_alu.vhd
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-- Date: Sun Mar 3 09:47:29 2024
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-- Author: Yannick Reiß
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-- E-Mail: yannick.reiss@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library std;
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use std.textio.all;
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library work;
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entity alu_tb is
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end alu_tb;
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architecture Testbench of alu_tb is
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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signal operator : std_logic_vector(5 downto 0) := (others => '0');
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signal operand1 : std_logic_vector(7 downto 0) := (others => '0');
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signal operand2 : std_logic_vector(7 downto 0) := (others => '0');
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signal result : std_logic_vector(7 downto 0) := (others => '0');
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begin
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uut : entity work.alu(Logic)
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port map (
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operator => operator,
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operand1 => operand1,
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operand2 => operand2,
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result => result
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);
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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testing : process
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variable lineBuffer : line;
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begin
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wait until rising_edge(clk);
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write(lineBuffer, string'("Starting the simulator"));
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writeline(output, lineBuffer);
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-- Testcases
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for i in 1 to 20 loop
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operand1 <= std_logic_vector(to_unsigned(i, 8));
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operand2 <= std_logic_vector(to_unsigned(20 - i, 8));
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operator <= "001101";
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wait for 10 ns;
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-- Not
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if not (result = not operand1) then
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write(lineBuffer, string'("Error on Not"));
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writeline(output, lineBuffer);
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end if;
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-- Parity
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operator <= "000100";
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wait for 10 ns;
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end loop;
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write(lineBuffer, string'("end of simulator"));
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writeline(output, lineBuffer);
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wait;
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end process;
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end Testbench;
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