First part of alu implementation

alu.vhd

@@ -8,11 +8,11 @@ use ieee.numeric_std.all;
 
 -- Entity ALU: Calculate result
 entity ALU is
-    port(
-        operator	:	in	std_logic_vector(3 downto 0);
-		operand1    :   in  std_logic_vector(2 downto 0);
-        operand2    :   in  std_logic_vector(2 downto 0);
-        result      :   out std_logic_vector(7 downto 0)
+  port(
+    operator : in  std_logic_vector(5 downto 0);
+    operand1 : in  std_logic_vector(7 downto 0);
+    operand2 : in  std_logic_vector(7 downto 0);
+    result   : out std_logic_vector(7 downto 0)
     );
 end ALU;
 
@@ -20,9 +20,43 @@ end ALU;
 architecture Logic of ALU is
 
 begin
-    -- Process Calculate
-    Calculate : process (all) -- runs only, when all changed
-    begin
-    end process;
-
+  -- Process Calculate
+  Calculate : process (all)
+  begin
+    case operator is
+      when "000000" => result <= not operand1;   -- Not op1
+      when "000100" =>
+        for i in operand1'range loop
+          result(i) <= operand1(i) xor operand2(i);
+        end loop;  -- Par op1
+      when "001000" => result <= (others => '0');        -- Cnt op1
+      when "001101" => result <= operand1 and operand2;  -- And op1
+      when "010001" => result <= operand1 or operand2;   -- Or op1
+      when "010101" => result <= operand1 xor operand2;  -- Xor op1
+      when "011001" => result <= operand2;       -- Mov op1
+      when "011101" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2))));  -- Sl op1
+      when "100001" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2))));  -- Sr op1
+      when "000010" => result <= std_logic_vector(unsigned(operand1) + unsigned(operand2));  -- Add op1
+      when "000110" => result <= std_logic_vector(signed(operand1) - signed(operand2));  -- Sub op1
+      when "000011" =>
+        if unsigned(operand1) = unsigned(operand2) then
+          result <= "00000001";
+        else
+          result <= (others => '0');
+        end if;  -- Seq op1
+      when "000111" =>
+        if signed(operand1) < signed(operand2) then
+          result <= "00000001";
+        else
+          result <= (others => '0');
+        end if;  -- Slt op1
+      when "001011" =>
+        if unsigned(operand1) < unsigned(operand2) then
+          result <= "00000001";
+        else
+          result <= (others => '0');
+        end if;  -- Sltu op1
+      when others => result <= (others => '0');  -- Default to nop operation
+    end case;
+  end process;
 end Logic;