122 lines
3.3 KiB
VHDL
122 lines
3.3 KiB
VHDL
-- tb_alu.vhd
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-- Date: Wed Jan 31 11:39:58 2024
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-- Author: Yannick Reiß
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-- E-Mail: schnick@nickr.eu
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity tb_alu is
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end tb_alu;
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architecture Testbench of tb_alu is
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signal alu_op : std_logic_vector(3 downto 0);
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signal input1 : std_logic_vector(15 downto 0);
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signal input2 : std_logic_vector(15 downto 0);
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signal result : std_logic_vector(15 downto 0);
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-- Helper procedure to print error message
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procedure print_error(msg : string) is
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begin
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report "Error: " & msg;
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end procedure;
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-- Helper procedure to check if the result is as expected
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procedure check_result(expected : std_logic_vector) is
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begin
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if result /= expected then
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print_error("Unexpected result. Expected: " & to_string(expected) & " Got: " & to_string(result));
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end if;
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end procedure;
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begin
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uut : entity work.Alu(Implementation)
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port map(
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alu_op => alu_op,
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input1 => input1,
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input2 => input2,
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result => result
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);
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Trigger : process
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begin
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-- Test ADD operation
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alu_op <= "0000";
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input1 <= "0000000000000000";
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input2 <= "0000000000000000";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000000");
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-- Test SUB operation
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alu_op <= "0010";
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input1 <= "0000000000000100";
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input2 <= "0000000000000001";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000011");
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-- Test SLL operation
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alu_op <= "0011";
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input1 <= "0000000000000001";
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input2 <= "0000000000000010";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000100");
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-- Test SLT operation
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alu_op <= "0100";
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input1 <= "0000000000000001";
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input2 <= "0000000000000010";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000000");
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-- Test SLTU operation
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alu_op <= "0101";
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input1 <= "0000000000000010";
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input2 <= "0000000000000001";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000001");
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-- Test XOR operation
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alu_op <= "0110";
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input1 <= "0000000000001010";
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input2 <= "0000000000001100";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000110");
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-- Test SRL operation
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alu_op <= "0111";
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input1 <= "0000000000001100";
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input2 <= "0000000000000001";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000110");
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-- Test SRA operation
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alu_op <= "1000";
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input1 <= "0000000000001111";
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input2 <= "0000000000000001";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000001111");
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-- Test OR operation
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alu_op <= "1010";
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input1 <= "0000000000001010";
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input2 <= "0000000000000101";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000001111");
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-- Test AND operation
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alu_op <= "1011";
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input1 <= "0000000000001010";
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input2 <= "0000000000000101";
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wait for 1 ns; -- Allow for processing
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check_result("0000000000000000");
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-- Print test successful if no errors occurred
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report "Test successful";
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wait;
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end process Trigger;
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end Testbench;
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