60 lines
1.2 KiB
VHDL
60 lines
1.2 KiB
VHDL
-- tb_bfpu
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-- 2023-10-04
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-- Author: Yannick Reiß
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-- E-Mail: yannick.reiss@protonmail.ch
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-- Copyright: MIT
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-- Content: Entity tb_bfpu - Run bfpu for testbench.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library std;
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use std.textio.all;
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entity bfpu_tb is
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end bfpu_tb;
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architecture implementation of bfpu_tb is
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-- input
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signal clk : std_logic;
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signal sw : std_logic_vector(7 downto 0);
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-- output
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signal debug : std_logic_vector(7 downto 0);
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signal led : std_logic_vector(7 downto 0);
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constant clk_period : time := 10 ns;
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begin
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uut : entity work.bfpu(arch)
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port map (
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clk => clk,
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sw => sw,
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debug => debug,
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led => led);
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sw <= "00001011";
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-- Clock process definitions
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period / 2;
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clk <= '1';
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wait for clk_period / 2;
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end process;
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-- Process stim_proc
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stim_proc : process
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variable lineBuffer : line;
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begin
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write(lineBuffer, string'("Start the simulator"));
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writeline(output, lineBuffer);
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wait;
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end process;
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end implementation ; -- implementation
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