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brainfuck_processor
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Fix jumping bug

This commit is contained in:
Yannick Reiß 2023-10-05 08:49:21 +02:00
parent b530f66702
commit a39b94c26f
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GPG Key ID: 5A3AF456F0A0338C
3 changed files with 70 additions and 50 deletions
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6
fpga/src/bfpu.vhd
View File

@ -73,6 +73,7 @@ architecture arch of bfpu is
component branch
port(
clk : in std_logic;
state : in std_logic;
instruction : in std_logic_vector(2 downto 0);
instr_addr : in std_logic_vector(7 downto 0);
cell_value : in std_logic_vector(7 downto 0);
@ -85,8 +86,8 @@ architecture arch of bfpu is
end component;
signal s_clk : std_logic;
signal s_in : std_logic_vector(7 downto 0);
signal s_out : std_logic_vector(7 downto 0);
signal s_in : std_logic_vector(7 downto 0) := (others => '0');
signal s_out : std_logic_vector(7 downto 0) := (others => '0');
signal s_instrAddr : std_logic_vector(7 downto 0) := "00000000";
signal s_instruction : std_logic_vector(2 downto 0) := "000";
@ -184,6 +185,7 @@ begin
branch_bf : branch
port map(
clk => s_clk,
state => processor_state,
instruction => s_instruction,
instr_addr => s_instrAddr,
cell_value => s_cell_out,

82
fpga/src/branch.vhd
View File

@ -12,6 +12,7 @@ use ieee.numeric_std.all;
entity branch is
port(
clk : in std_logic;
state : in std_logic;
instruction : in std_logic_vector(2 downto 0);
instr_addr : in std_logic_vector(7 downto 0);
cell_value : in std_logic_vector(7 downto 0);
@ -35,66 +36,83 @@ architecture impl of branch is
begin
-- Process p_branch: set skip to true
p_branch : process (clk, skip_internal, instruction, cell_value)
-- Process branch_compute Thing that does things.
branch_compute : process (all) -- runs only, when all changed
begin
if rising_edge(clk) then
if instruction = "110" and unsigned(cell_value) = 0 and unsigned(nested) = 0 and skip_internal = '0' then
skip_internal <= '1';
-- set addr_stack
if skip = '0' then
-- pop part 1
-- push part 2
if state = '1' and instruction = "110" then
addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr;
end if;
end if;
-- set skip to false
if instruction = "111" and unsigned(nested) = 0 and skip_internal = '1' then
skip_internal <= '0';
end if;
-- set nested
if state = '0' and skip_internal = '1' then
-- Process p_nest : raise nest by one as [ is passed
if instruction = "110" and skip_internal = '1' then
-- deeper nest
if instruction = "110" then
nested <= std_logic_vector(unsigned(nested) + 1);
end if;
-- Process p_unnest : lower nest, as ] is passed
if instruction = "111" and unsigned(nested) > 0 and skip_internal = '1' then
-- nested loop ended
if instruction = "111" then
nested <= std_logic_vector(unsigned(nested) - 1);
end if;
end if;
-- Process p_push : raise stack and push address
if instruction = "110" and unsigned(cell_value) > 0 and skip_internal = '0' then
if pc_enable_internal = '0' then
-- restore push_state and push address
addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr;
pc_enable_internal <= '1';
-- set skip
-- on instruction [
if instruction = "110" and state = '0' then
if unsigned(cell_value) > 0 and not ( skip_internal = '1' or unsigned(nested) > 0 ) then
skip_internal <= '0';
else
-- raise stack, disable pc and unset push_state
stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1);
pc_enable_internal <= '0';
skip_internal <= '1';
end if;
end if;
-- Process p_pop : read address to jump address and lower stack
if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '1' then
if pc_enable_internal = '0' then
-- set address to pc_out, disable pc and unset push_state
-- pc_out <= addr_stack(to_integer(unsigned(stack_ptr))); TODO: restore if error with continuous assignment
pc_enable_internal <= '1';
-- on instruction ]
if state = '0' and instruction = "111" then
if skip_internal = '1' and unsigned(nested) > 0 then
skip_internal <= '1';
else
-- set pc to enabled, restore push_state and lower stack
pc_enable_internal <= '0';
skip_internal <= '0';
end if;
end if;
-- set stack_ptr
if skip_internal = '0' then
-- pop part 2
if state = '1' and instruction = "111" then
stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1);
end if;
-- push part 1
if state = '0' and instruction = "110" then
stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1);
end if;
end if;
-- regulate jump
if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' and pc_enable_internal = '1' then
-- set pc_enable
pc_enable_internal <= not state;
-- set jump
if instruction = "111" and skip = '0' and state = '0' then
jump <= '1';
else
jump <= '0';
end if;
end if;
end process;
-- connect signals to pins
skip <= skip_internal;
pc_enable <= pc_enable_internal;
pc_out <= addr_stack(to_integer(unsigned(stack_ptr)));

4
fpga/src/instructionMemory.vhd
View File

@ -20,8 +20,8 @@ end instructionMemory;
architecture arch of instructionMemory is
type imem is array(0 to 255) of std_logic_vector(2 downto 0);
-- ,>+<.>.
signal memory : imem := (b"100", b"000", b"010", b"001", b"101", b"000", b"101", others => "000");
-- +[+.]
signal memory : imem := (b"010", b"110", b"010", b"101", b"111", others => "000");
begin
-- Process clk_read
-- clk_read : process (clk) -- runs only, when clk changed