Init TinyTapeout repository
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12
TinyTapeout/src/bfpu.v
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12
TinyTapeout/src/bfpu.v
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module tt_um_yannickreiss_bfpu(input wire [7:0] ui_in, // Dedicated inputs
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output wire [7:0] uo_out, // Dedicated outputs
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input wire [7:0] uio_in, // IOs: Input path
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output wire [7:0] uio_out, // IOs: Output path
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output wire [7:0] uio_oe, // IOs: Enable path (active high: 0 = input, 1 = output
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input wire ena,
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input wire clk,
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input wire rst_n);
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endmodule
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116
TinyTapeout/src/cells.v
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116
TinyTapeout/src/cells.v
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/*
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This file provides the mapping from the Wokwi modules to Verilog HDL
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It's only needed for Wokwi designs
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*/
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`define default_netname none
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// custom cells
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module reg_cell (input wire clk,
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input wire d,
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output wire q);
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reg register;
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always @(posedge clk) begin
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register = d;
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end
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assign q = register;
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endmodule // reg_cell
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// TinyTapeout cells
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module buffer_cell (
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input wire in,
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output wire out
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);
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assign out = in;
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endmodule
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module and_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = a & b;
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endmodule
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module or_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = a | b;
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endmodule
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module xor_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = a ^ b;
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endmodule
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module nand_cell (
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input wire a,
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input wire b,
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output wire out
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);
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assign out = !(a&b);
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endmodule
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module not_cell (
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input wire in,
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output wire out
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);
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assign out = !in;
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endmodule
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module mux_cell (
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input wire a,
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input wire b,
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input wire sel,
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output wire out
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);
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assign out = sel ? b : a;
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endmodule
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module dff_cell (
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input wire clk,
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input wire d,
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output reg q,
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output wire notq
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);
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assign notq = !q;
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always @(posedge clk)
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q <= d;
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endmodule
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module dffsr_cell (
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input wire clk,
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input wire d,
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input wire s,
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input wire r,
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output reg q,
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output wire notq
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);
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assign notq = !q;
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always @(posedge clk or posedge s or posedge r) begin
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if (r)
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q <= 0;
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else if (s)
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q <= 1;
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else
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q <= d;
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end
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endmodule
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62
TinyTapeout/src/config.tcl
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62
TinyTapeout/src/config.tcl
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# PLEASE DO NOT EDIT THIS FILE!
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# If you get stuck with this config, please open an issue or get in touch via the discord.
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# Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html
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# User config
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set script_dir [file dirname [file normalize [info script]]]
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# read some user config that is written by the setup.py program.
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# - the name of the module is defined
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# - the list of source files
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source $::env(DESIGN_DIR)/user_config.tcl
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# save some time
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set ::env(RUN_KLAYOUT_XOR) 0
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set ::env(RUN_KLAYOUT_DRC) 0
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# don't put clock buffers on the outputs
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set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
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# allow use of specific sky130 cells
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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# reduce wasted space
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set ::env(TOP_MARGIN_MULT) 1
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set ::env(BOTTOM_MARGIN_MULT) 1
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set ::env(LEFT_MARGIN_MULT) 6
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set ::env(RIGHT_MARGIN_MULT) 6
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# absolute die size
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set ::env(FP_SIZING) absolute
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set ::env(PL_BASIC_PLACEMENT) {0}
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set ::env(GRT_ALLOW_CONGESTION) "1"
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# otherwise fails on small designs at global placement
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set ::env(GRT_CELL_PADDING) "4"
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set ::env(FP_IO_HLENGTH) 2
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set ::env(FP_IO_VLENGTH) 2
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# use alternative efabless decap cells to solve LI density issue
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set ::env(DECAP_CELL) "\
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sky130_fd_sc_hd__decap_3 \
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sky130_fd_sc_hd__decap_4 \
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sky130_fd_sc_hd__decap_6 \
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sky130_fd_sc_hd__decap_8 \
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sky130_ef_sc_hd__decap_12"
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# clock
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set ::env(CLOCK_TREE_SYNTH) 1
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# period is in ns, so 20ns == 50mHz
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set ::env(CLOCK_PERIOD) "20"
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set ::env(CLOCK_PORT) {clk}
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# hold/slack margin
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# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8
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# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8
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# don't use power rings or met5
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set ::env(DESIGN_IS_CORE) 0
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set ::env(RT_MAX_LAYER) {met4}
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