85 lines
1.9 KiB
VHDL
85 lines
1.9 KiB
VHDL
-- tb_decoder.vhd
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-- Created on: Di 6. Dez 10:50:02 CET 2022
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-- Author(s): Yannick Reiß, Car Ries, Alexander Graf
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-- Content: Testbench for decoder (NOT AUTOMATED, ONLY STIMULI)
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.uniform;
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library work;
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use work.riscv_types.all;
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library std;
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use std.textio.all;
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-- Entity decoder_tb: dummy entity for decoder
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entity decoder_tb is
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end decoder_tb;
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-- Architecture testingdecoder of decoder_tb: testing instruction decode
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architecture testingdecoder of decoder_tb is
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-- clk
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signal clk : std_logic;
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constant clk_period : time := 10 ns;
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-- inputs
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signal instrDecode : instruction;
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-- outputs
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signal aluOpCode : uOP;
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signal regOp1 : reg_idx;
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signal regOp2 : reg_idx;
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signal regWrite : reg_idx;
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begin
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uut : entity work.decoder(decode)
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port map (
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instrDecode => instrDecode,
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op_code => aluOpCode,
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regOp1 => regOp1,
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regOp2 => regOp2,
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regWrite => regWrite);
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-- clk-prog
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clk_process : process -- runs only, when changed
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Process stim_proc stimulate uut
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stim_proc : process -- runs only, when changed
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variable lineBuffer : line;
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begin
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write(lineBuffer, string'("Start the simulator"));
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writeline(output, lineBuffer);
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wait for 5 ns;
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-- add x9, x0, x3
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instrDecode <= "00000000001100000000010010110011";
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wait for 10 ns;
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-- add x1, x2, x3
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instrDecode <= "00000000001100010000000010110011";
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wait for 10 ns;
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-- sll x1, x0, x2
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instrDecode <= "00000000001000000001000010110011";
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wait for 10 ns;
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-- sub x6, x3, x1
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instrDecode <= "01000000000100011000001100110011";
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wait for 10 ns;
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-- nop x6, x3, x1
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instrDecode <= "01000000000100011000001100110111";
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wait for 10 ns;
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wait;
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end process;
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end testingdecoder;
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