Reset in Register

src/cpu.vhd

@@ -327,11 +327,10 @@ begin
         when stEXEC => s_cycle_cnt <= stWB;
         when others => s_cycle_cnt <= stIF;
       end case;
-    else
+    end if;
     if falling_edge(reset) then
       s_cycle_cnt <= stIF;
     end if;
-    end if;
   end process pc_cycle_control;
 
 end implementation;

src/pc.vhd

@@ -26,8 +26,11 @@ architecture pro_count of pc is
   signal addr_out      : ram_addr_t := (others => '0');
   signal addr_out_plus : ram_addr_t := (others => '0');
 begin
-  process (clk)
+  process (clk, reset)
   begin
+    if falling_edge(reset) then
+      addr_out <= (others => '0');
+    else
       if rising_edge(clk) then
         if en_pc = "1" then
           -- count 
@@ -39,13 +42,6 @@ begin
           end if;
         end if;
       end if;
-  end process;
-
-  process (reset)
-  begin
-    if falling_edge(reset) then
-      addr_out      <= (others => '0');
-      addr_out_plus <= (others => '0');
     end if;
   end process;
 

src/registers.vhd

@@ -40,8 +40,11 @@ architecture structure of registers is
 begin
 
     -- react only on clock changes
-    process (clk)                       -- runs only, when clk changed
+    process (clk, reset)                -- runs only, when clk changed
     begin
+        if falling_edge(reset) then
+            registerbench <= initRegs;
+        else
             if rising_edge(clk) then
                 -- check if write is enabled
                 if to_integer(unsigned(write_enable)) = 1 then
@@ -50,13 +53,6 @@ begin
                 end if;
                 registerbench(0) <= std_logic_vector(to_unsigned(0, wordWidth));
             end if;
-    end process;
-
-    -- reset if reset is activated
-    process (reset)
-    begin
-        if falling_edge(reset) then
-            registerbench <= initRegs;
         end if;
     end process;