Init

tb/tb_lut.vhd

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+-- tb_lut.vhd
+-- Created on: Mo 12. Dez 10:45:36 CET 2022
+-- Author(s): Yannick Reiss
+-- Content: Testbench for Taperead and Tapewrite
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+-- Entity lut_tb: Testing unit (wrapper)
+entity lut_tb is
+end lut_tb;
+
+-- Architecture  of : test read and write operations
+architecture testing of lut_tb is
+		-- Clock
+		signal clk : std_logic;
+		constant clk_period : time := 10 ns;
+
+		-- Inputs
+        signal vec_in : std_logic_vector(3 downto 0) := "0000";
+        signal prog_ena : std_logic := '0';
+        signal truth_table : std_logic_vector(15 downto 0) := (others => '0');
+
+		-- Outputs
+        signal sig_out : std_logic := '0';
+
+begin
+
+		-- Instantiate the Unit Under Test (UUT)
+		-- Entity work.lut(Behavior): Unit to test
+		uut : entity work.lut(Behavior)
+				port map (
+                    clk => clk,
+                    input_vector => vec_in,
+                    program_enable => prog_ena,
+                    truth_table => truth_table,
+                    output_signal => sig_out
+					);
+
+		-- Process clk_process  Clock process definitions
+		clk_process : process -- runs only, when  changed
+		begin
+				clk <= '0';
+				wait for clk_period/2;
+				clk <= '1';
+				wait for clk_period/2;
+		end process;
+
+		-- Process stim_proc
+		stim_proc : process -- runs only, when  changed
+		begin
+
+		-- wait for the frist rising edge
+		wait until rising_edge(clk);
+
+        -- Set up the LUT
+        truth_table <= "1111000000000000";
+        prog_ena <= '1';
+        wait for 5 ns;
+        prog_ena <= '0';
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0000";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0001";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0010";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0011";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0100";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0101";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0110";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "0111";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1000";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1001";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1010";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1011";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1100";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1101";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1110";
+        wait for 5 ns;
+
+        -- Test
+        vec_in <= "1111";
+        wait for 5 ns;
+
+		-- Testing memory
+				wait for 5 ns;
+				wait;
+		end process;
+
+end ;