Init

src/lut.vhd

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+-- lut.vhd
+-- Created on: Mi 28. Dez 13:36:43 CET 2022
+-- Author(s): Yannick Reiß
+-- Content:  Entity lut
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Entity lut: multiply two words
+entity lut is
+  port(
+    clk             :   in  std_logic;
+    input_vector    :   in  std_logic_vector(3 downto 0);
+    program_enable  :   in  std_logic;
+    truth_table     :   in  std_logic_vector(15 downto 0);
+    output_signal   :   out std_logic
+    );
+end lut;
+
+-- Architecture Behavior of lut: multiply two words
+architecture Behavior of lut is
+    signal internal_truth_table : std_logic_vector(15 downto 0) := (others => '0');
+begin
+
+    -- Process program
+    program : process (all) -- runs only, when all changed
+    begin
+        if rising_edge(clk) then
+            if program_enable = '1' then
+                internal_truth_table <= truth_table;
+            end if;
+        end if;
+    end process;
+
+    output_signal <= truth_table(to_integer(unsigned(input_vector)));
+
+end Behavior;