-- alu.vhd
-- Created on: Sa 2. Mär 15:48:05 CET 2024
-- Author(s): Yannick Reiß
-- Content: ALU entity
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Entity ALU: Calculate result
entity ALU is
  port(
    operator : in  std_logic_vector(5 downto 0);
    operand1 : in  std_logic_vector(7 downto 0);
    operand2 : in  std_logic_vector(7 downto 0);
    result   : out std_logic_vector(7 downto 0)
    );
end ALU;

-- Architecture Logic of ALU: Asynchronous calculation
architecture Logic of ALU is
  signal parity : std_logic                    := '0';
  signal count  : std_logic_vector(7 downto 0) := (others => '0');
begin

  set_parity : process(operand1(0), operand1(1), operand1(2), operand1(3),
                       operand1(4), operand1(5), operand1(6), operand1(7))
  begin
    parity <= operand1(7) xor operand1(6) xor operand1(5) xor operand1(4) xor operand1(3) xor operand1(2) xor operand1(1) xor operand1(0);
  end process set_parity;

  set_count : process(all)
  begin
    count <= std_logic_vector(unsigned(count));
  end process set_count;


  -- Process Calculate
  Calculate : process (operand1, operand2, operator, parity)
  begin
    case operator is
      when "000000" => result <= operand1 xor "11111111";  -- Not op1
      when "000100" => result <= "0000000" & parity;       -- Par op1
      when "001000" => result <= (others => '0');          -- Cnt op1
      when "001101" => result <= operand1 and operand2;    -- And op1
      when "010001" => result <= operand1 or operand2;     -- Or op1
      when "010101" => result <= operand1 xor operand2;    -- Xor op1
      when "011001" => result <= operand2;       -- Mov op1
      when "011101" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) sll to_integer(unsigned(operand2))));  -- Sl op1
      when "100001" => result <= std_logic_vector(to_stdlogicvector(to_bitvector(operand1) srl to_integer(unsigned(operand2))));  -- Sr op1
      when "000010" => result <= std_logic_vector(unsigned(operand1) + unsigned(operand2));  -- Add op1
      when "000110" => result <= std_logic_vector(signed(operand1) - signed(operand2));  -- Sub op1
      when "000011" =>
        if unsigned(operand1) = unsigned(operand2) then
          result <= "00000001";
        else
          result <= (others => '0');
        end if;  -- Seq op1
      when "000111" =>
        if signed(operand1) < signed(operand2) then
          result <= "00000001";
        else
          result <= (others => '0');
        end if;  -- Slt op1
      when "001011" =>
        if unsigned(operand1) < unsigned(operand2) then
          result <= "00000001";
        else
          result <= (others => '0');
        end if;  -- Sltu op1
      when others => result <= (others => '0');  -- Default to nop operation
    end case;
  end process;
end Logic;