From 1b4f753c5454a3fc6b2b052694b7f954c13ad8a0 Mon Sep 17 00:00:00 2001 From: yannickreiss Date: Wed, 4 Oct 2023 11:27:25 +0200 Subject: [PATCH] First working implementation --- fpga/constrainits.xdc | 48 +++++++++++++++++----------------- fpga/src/alu.vhd | 30 ++++++++++++++++++--- fpga/src/bfpu.vhd | 2 ++ fpga/src/branch.vhd | 46 ++++++++++---------------------- fpga/src/cellMemory.vhd | 2 +- fpga/src/instructionMemory.vhd | 5 ++-- fpga/src/memoryPointer.vhd | 2 +- fpga/src/programCounter.vhd | 2 +- 8 files changed, 73 insertions(+), 64 deletions(-) diff --git a/fpga/constrainits.xdc b/fpga/constrainits.xdc index 463edd0..9dec428 100755 --- a/fpga/constrainits.xdc +++ b/fpga/constrainits.xdc @@ -86,30 +86,30 @@ set_property PACKAGE_PIN U7 [get_ports {led[6]}] #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 set_property PACKAGE_PIN U6 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] -##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 -#set_property PACKAGE_PIN V4 [get_ports {led[8]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] -##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 -#set_property PACKAGE_PIN U3 [get_ports {led[9]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] -##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 -#set_property PACKAGE_PIN V1 [get_ports {led[10]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] -##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 -#set_property PACKAGE_PIN R1 [get_ports {led[11]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] -##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 -#set_property PACKAGE_PIN P5 [get_ports {led[12]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] -##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 -#set_property PACKAGE_PIN U1 [get_ports {led[13]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] -##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 -#set_property PACKAGE_PIN R2 [get_ports {led[14]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] -##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 -#set_property PACKAGE_PIN P2 [get_ports {led[15]}] -# set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] +#Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 +set_property PACKAGE_PIN V4 [get_ports {debug[0]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[0]}] +#Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 +set_property PACKAGE_PIN U3 [get_ports {debug[1]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[1]}] +#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 +set_property PACKAGE_PIN V1 [get_ports {debug[2]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[2]}] +#Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 +set_property PACKAGE_PIN R1 [get_ports {debug[3]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[3]}] +#Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 +set_property PACKAGE_PIN P5 [get_ports {debug[4]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[4]}] +#Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 +set_property PACKAGE_PIN U1 [get_ports {debug[5]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[5]}] +#Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 +set_property PACKAGE_PIN R2 [get_ports {debug[6]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[6]}] +#Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 +set_property PACKAGE_PIN P2 [get_ports {debug[7]}] + set_property IOSTANDARD LVCMOS33 [get_ports {debug[7]}] ##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R #set_property PACKAGE_PIN K5 [get_ports {rgb[0]}] diff --git a/fpga/src/alu.vhd b/fpga/src/alu.vhd index 35e1808..5f791b6 100644 --- a/fpga/src/alu.vhd +++ b/fpga/src/alu.vhd @@ -24,40 +24,64 @@ end alu; -- Architecture implementation of alu: implements table architecture implementation of alu is - + signal buffer_out : std_logic_vector(7 downto 0) := (others => '0'); begin -- Process p_instruction - p_instruction : process (instruction) -- runs only, when instruction changed + p_instruction : process (extern_in, instruction, old_cell, old_pointer) begin case instruction is when "000" => enable_cell <= '0'; enable_ptr <= '1'; new_pointer <= std_logic_vector(unsigned(old_pointer) + 1); + + new_cell <= old_cell; + buffer_out <= "00000000"; when "001" => enable_cell <= '0'; enable_ptr <= '1'; new_pointer <= std_logic_vector(unsigned(old_pointer) - 1); + + new_cell <= old_cell; + buffer_out <= "00000000"; when "010" => enable_cell <= '1'; enable_ptr <= '0'; new_cell <= std_logic_vector(unsigned(old_cell) + 1); + + new_pointer <= old_pointer; + buffer_out <= "00000000"; when "011" => enable_cell <= '1'; enable_ptr <= '0'; new_cell <= std_logic_vector(unsigned(old_cell) - 1); + + new_pointer <= old_pointer; + buffer_out <= "00000000"; when "100" => enable_cell <= '1'; enable_ptr <= '0'; new_cell <= extern_in; + + new_pointer <= old_pointer; + buffer_out <= "00000000"; when "101" => enable_cell <= '0'; enable_ptr <= '0'; - extern_out <= old_cell; + buffer_out <= old_cell; + + new_pointer <= old_pointer; + new_cell <= old_cell; when others => enable_cell <= '0'; enable_ptr <= '0'; + + new_pointer <= old_pointer; + new_cell <= old_cell; + buffer_out <= "00000000"; end case; end process; + extern_out <= buffer_out; + end implementation; diff --git a/fpga/src/bfpu.vhd b/fpga/src/bfpu.vhd index ff6d86c..ce188a0 100644 --- a/fpga/src/bfpu.vhd +++ b/fpga/src/bfpu.vhd @@ -11,6 +11,7 @@ entity bfpu is port( clk : in std_logic; -- board clock sw : in std_logic_vector(7 downto 0); -- Input for instruction , + debug : out std_logic_vector(7 downto 0); -- Value of currently selected logic cell. led : out std_logic_vector(7 downto 0) -- Output for instruction . ); end bfpu; @@ -169,5 +170,6 @@ begin s_enable_ptr <= s_skip and s_enable_ptr_o; s_enable_cells <= s_skip and s_enable_cells_o; + debug <= s_cell_out; end arch; diff --git a/fpga/src/branch.vhd b/fpga/src/branch.vhd index cf7c1c7..cafd8d8 100644 --- a/fpga/src/branch.vhd +++ b/fpga/src/branch.vhd @@ -6,6 +6,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +-- TODO: CHECK PUSH AND POP AND THE PHASES/STATES OF PC_ENABLE + -- Entity branch: branch entity branch is port( @@ -29,88 +31,68 @@ architecture impl of branch is signal nested : std_logic_vector(7 downto 0) := (others => '0'); -- count nested loops signal skip_internal : std_logic := '0'; signal stack_ptr : std_logic_vector(7 downto 0) := (others => '0'); - signal push_state : std_logic := '1'; begin - -- Process p_skip: set skip to true - p_skip : process (clk) + -- Process p_branch: set skip to true + p_branch : process (clk, skip_internal, instruction, cell_value) begin if rising_edge(clk) then if instruction = "110" and unsigned(cell_value) = 0 and unsigned(nested) = 0 and skip_internal = '0' then skip_internal <= '1'; end if; end if; - end process; - -- Process p_continue: set skip to false - p_continue : process (clk) - begin + -- set skip to false if rising_edge(clk) then if instruction = "111" and unsigned(nested) = 0 and skip_internal = '1' then skip_internal <= '0'; end if; end if; - end process; - -- Process p_nest : raise nest by one as [ is passed - p_nest : process (clk) - begin + -- Process p_nest : raise nest by one as [ is passed if rising_edge(clk) then if instruction = "110" and skip_internal = '1' then nested <= std_logic_vector(unsigned(nested) + 1); end if; end if; - end process; - -- Process p_unnest : lower nest, as ] is passed - p_unnest : process (clk) - begin + -- Process p_unnest : lower nest, as ] is passed if rising_edge(clk) then if instruction = "111" and unsigned(nested) > 0 and skip_internal = '1' then nested <= std_logic_vector(unsigned(nested) - 1); end if; end if; - end process; - -- Process p_push : raise stack and push address - p_push : process (clk) - begin + -- Process p_push : raise stack and push address if rising_edge(clk) and instruction = "110" and unsigned(cell_value) > 0 and skip_internal = '0' then - if push_state = '0' then + if pc_enable = '0' then -- restore push_state and push address addr_stack(to_integer(unsigned(stack_ptr))) <= instr_addr; - push_state <= '1'; pc_enable <= '1'; else -- raise stack, disable pc and unset push_state stack_ptr <= std_logic_vector(unsigned(stack_ptr) + 1); pc_enable <= '0'; - push_state <= '0'; end if; end if; - end process; - -- Process p_pop : read address to jump address and lower stack - p_pop : process (clk) - begin + -- Process p_pop : read address to jump address and lower stack if rising_edge(clk) and instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' then - if push_state = '1' then + if pc_enable = '0' then -- set address to pc_out, disable pc and unset push_state pc_out <= addr_stack(to_integer(unsigned(stack_ptr))); - pc_enable <= '0'; - push_state <= '0'; + pc_enable <= '1'; else -- set pc to enabled, restore push_state and lower stack - pc_enable <= '1'; - push_state <= '1'; + pc_enable <= '0'; stack_ptr <= std_logic_vector(unsigned(stack_ptr) - 1); end if; end if; -- regulate jump if rising_edge(clk) then - if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' and push_state = '0' then + if instruction = "111" and unsigned(cell_value) > 0 and skip_internal = '0' and pc_enable = '1' then jump <= '1'; else jump <= '0'; diff --git a/fpga/src/cellMemory.vhd b/fpga/src/cellMemory.vhd index b7da2d6..4ce7488 100644 --- a/fpga/src/cellMemory.vhd +++ b/fpga/src/cellMemory.vhd @@ -28,7 +28,7 @@ architecture arch of cellblock is begin -- Process clk_read - clk_read : process (clk) -- runs only, when clk changed + clk_read : process (clk, enable) -- runs only, when clk changed begin if rising_edge(clk) and enable = '1' then diff --git a/fpga/src/instructionMemory.vhd b/fpga/src/instructionMemory.vhd index aa9c6c7..b30f97d 100644 --- a/fpga/src/instructionMemory.vhd +++ b/fpga/src/instructionMemory.vhd @@ -19,9 +19,10 @@ end instructionMemory; -- Architecture arch of instructionMemory: read on every clock cycle to instruction. architecture arch of instructionMemory is + type imem is array(0 to 255) of std_logic_vector(2 downto 0); - - signal memory : imem := (b"000", b"001", b"010", b"011", b"100", b"101", b"110", b"111", others => "000"); + -- [+.] + signal memory : imem := (b"110", b"010", b"101", b"111", others => "000"); begin -- Process clk_read clk_read : process (clk) -- runs only, when clk changed diff --git a/fpga/src/memoryPointer.vhd b/fpga/src/memoryPointer.vhd index 141395b..857afa6 100644 --- a/fpga/src/memoryPointer.vhd +++ b/fpga/src/memoryPointer.vhd @@ -23,7 +23,7 @@ architecture implement_ptr of ptr is begin -- Process Write set new_ptr - write : process (clk) -- runs only, when clk changed + write : process (clk, enable_ptr) -- runs only, when clk changed begin if rising_edge(clk) and enable_ptr = '1' then reg <= new_ptr; diff --git a/fpga/src/programCounter.vhd b/fpga/src/programCounter.vhd index 5846e07..22e1d69 100644 --- a/fpga/src/programCounter.vhd +++ b/fpga/src/programCounter.vhd @@ -23,7 +23,7 @@ architecture pc of program_counter is begin -- Process count - count : process (clk, enable, jmp) -- runs only, when clk, enable, jmp changed + count : process (clk, enable) -- runs only, when clk, enable, jmp changed begin if rising_edge(clk) and enable = '1' then if jmp = '1' then